Index: Makefile ================================================================== --- Makefile +++ Makefile @@ -2,23 +2,19 @@ # TRACE_LEVEL_INFO 4 # TRACE_LEVEL_WARNING 3 # TRACE_LEVEL_ERROR 2 # TRACE_LEVEL_FATAL 1 # TRACE_LEVEL_NO_TRACE 0 -TRACE_LEVEL = 5 +TRACE_LEVEL = 4 -TARGET = due +TARGET = stm32f405h -ifeq ($(TARGET), due) - include atmel.mk -else ifeq ($(TARGET), 4pi) - include atmel.mk + include atmel.mak else ifeq ($(TARGET), stm32f405h) - include stm32f405.mk -endif + include stm32f405.mak endif endif # List of C source files. @@ -33,11 +29,10 @@ CSRCS += src/mctrl_ringbuf.c CSRCS += src/stopgo_speed_planner_fixp32.c CSRCS += src/syscalls.c CSRCS += src/heater.c CSRCS += src/softpwm.c -CSRCS += src/sp200c.c # List of assembler source files. # ASSRCS = @@ -45,15 +40,16 @@ INCLUDES += -I. #INCLUDES += -Icmsis/sam3u/source/templates # Additional search paths for libraries. -# LIB_PATH += thirdparty/CMSIS/Lib/GCC +LIB_PATH = \ + thirdparty/CMSIS/Lib/GCC # List of libraries to use during linking. -LIBS += m -LIBS += c +LIBS = \ + m # arm_cortexM3l_math \ # Project type parameter: all, sram or flash PROJECT_TYPE = flash @@ -62,20 +58,20 @@ # add -g3. DBGFLAGS = -g # Application optimization used during compilation and linking: # -O0, -O1, -O2, -O3 or -Os -OPTIMIZATION = -O0 +OPTIMIZATION = -O3 # Extra flags to use when archiving. ARFLAGS = # Extra flags to use when assembling. ASFLAGS = # Extra flags to use when compiling. -CFLAGS += -mlong-calls -ffunction-sections -fdata-sections -flto -Wno-redundant-decls +CFLAGS += -mlong-calls -ffunction-sections # Extra flags to use when preprocessing. # # Preprocessor symbol definitions # To add a definition use the format "-D name[=definition]". @@ -91,14 +87,12 @@ CPPFLAGS += -D__Vendor_SysTickConfig=1 CPPFLAGS += -DM_PI=3.14159265358979323846264338327950288 # -D printf=iprintf # Extra flags to use when linking -#LDFLAGS = -nostartfiles $(TARGET_OPTS) -Wl,--gc-sections -# LDFLAGS += $(TARGET_OPTS) -Wl,--gc-sections --specs=nosys.specs -lnosys -lc -lnosys -# LDFLAGS += $(TARGET_OPTS) -Wl,--gc-sections --specs=rdimon.specs -lgcc -lc -lm -lrdimon -LDFLAGS += $(TARGET_OPTS) -Wl,--gc-sections --specs=nosys.specs +//LDFLAGS = -nostartfiles $(TARGET_OPTS) -Wl,--gc-sections +LDFLAGS = $(TARGET_OPTS) -Wl,--gc-sections # Tool to use to generate documentation from the source code DOCGEN ?= doxygen # Look for source files relative to the top-level source directory @@ -169,11 +163,10 @@ # Output documentation directory and configuration file. docdir := ../doxygen/html doccfg := ../doxygen/doxyfile.doxygen -# CROSS ?= /Users/dog/Applications/ARM-Toolchain/gcc-arm-none-eabi-5_4-2016q3/bin/arm-none-eabi- CROSS ?= /Users/dog/Applications/ARM-Toolchain/gcc-arm-none-eabi-4_8-2014q1/bin/arm-none-eabi- AR := $(CROSS)ar AS := $(CROSS)as CC := $(CROSS)gcc CPP := $(CROSS)gcc -E @@ -426,14 +419,10 @@ # upload via bossac. .PHONY: bossa bossa: all bossac -e -w -v -b --port="cu.usbmodemfa1241" $(project).bin -.PHONY: bossadue -bossadue: all - ../BOSSA/bin/bossac -e -w -v -b --port="cu.usbmodem1451" $(project).bin -R - # Debug the project in flash. .PHONY: debug_flash debug_flash: all $(GDB) -x "$(ASF_PATH)/$(DEBUG_SCRIPT_FLASH)" -ex "reset" -readnow -se $(TARGET_FLASH) @@ -492,11 +481,11 @@ ifeq ($(target_type),elf) # Link the object files into an ELF file. Also make sure the target is rebuilt # if the common Makefile.sam.in or project is changed. $(target): $(linker_script) $(MAKEFILE_PATH) $(obj-y) @echo $(MSG_LINKING) - $(LD) $(l_flags) $(obj-y) $(libflags-gnu-y) -o $@ + $(Q)$(LD) $(l_flags) $(obj-y) $(libflags-gnu-y) -o $@ @echo $(MSG_SIZE) $(Q)$(SIZE) -Ax $@ $(Q)$(SIZE) -Bx $@ endif endif @@ -541,52 +530,31 @@ # Rebuild the Doxygen generated documentation. .PHONY: rebuilddoc rebuilddoc: cleandoc doc -program: $(TARGET_FLASH) +program: $(OBJDIR)/$(PROJ_NAME).elf openocd -f program.cfg -.PHONY: kextu kextu: sudo kextunload -p -b com.apple.driver.AppleUSBFTDI sudo kextutil -b com.apple.driver.AppleUSBFTDI -p AppleUSBEFTDI-6010-1 sudo kextunload -p -b com.FTDI.driver.FTDIUSBSerialDriver sudo kextutil -b com.FTDI.driver.FTDIUSBSerialDriver -p AppleUSBEFTDI-6010-1 -.PHONY: kextl kextl: sudo kextload -b com.FTDI.driver.FTDIUSBSerialDriver sudo kextload -b com.apple.driver.AppleUSBFTDI oocd: openocd -f debug.cfg debug: $(GDB) --eval-command="target remote localhost:3333" $(TARGET_FLASH) - -rmCube: - rm -rf stm32/CMSIS - rm -rf stm32/STM32F4xx_HAL_Driver - rm -rf stm32/STM32_USB_Device_Library - rm -rf stm32/Inc - rm -rf stm32/Src - rm stm32/boards/stm32f405/STM32F405RGTx_FLASH.ld - + copyCube: - cp -a STM32F405-olimex/STM32F405-olimex/Drivers/CMSIS stm32/ - cp -a STM32F405-olimex/STM32F405-olimex/Drivers/STM32F4xx_HAL_Driver stm32/ - cp -a STM32F405-olimex/STM32F405-olimex/Middlewares/ST/STM32_USB_Device_Library stm32/ - cp -a STM32F405-olimex/STM32F405-olimex/Inc stm32/ - cp -a STM32F405-olimex/STM32F405-olimex/Src stm32/ - cp -a STM32F405-olimex/STM32F405-olimex/STM32F405RGTx_FLASH.ld stm32/boards/stm32f405/STM32F405RGTx_FLASH.ld - mv stm32/Src/main.c stm32/Src/stm32_main.c - perl -0p -i~ -e 's/^int main\(void\).*?\{(.*?)while \(1\).*?\{.*?\}.*?\}/int stm32_init\(void\)\n\{\1\n\}/igsm' stm32/Src/stm32_main.c - perl -0p -i~ -e 's/^(#define __Vendor_SysTickConfig 0U)/\/\/\1/igsm' stm32/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h - perl -0p -i~ -e 's/^(uint32_t HAL_SYSTICK_Config\(uint32_t TicksNumb\))/uint32_t SysTick_Config\(uint32_t TicksNumb\);\n\n\1/igsm' stm32/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c - perl -0p -i~ -e 's/^void SysTick_Handler\(void\)/void SysTick_Handler_unused(void)/igsm' stm32/Src/stm32f4xx_it.c - - #define __Vendor_SysTickConfig 0U -# sed -e "s/^int main(void)/int stm32_main(void)/" stm32/Src/stm32_main.c -# perl -pi -e 's/^int main\(void\)/void stm32_init\(void\)/igs' stm32/Src/stm32_main.c -# perl -pi -e 's/^int main\(void\).*\{(.*)while \(1\).*\{.*\}.*\}/int stm32_init\(void\).\n\{$1\}/igs' stm32/Src/stm32_main.c + cp -a STM32F405-olimex/STM32F405-olimex/Drivers/CMSIS stm32/CMSIS + cp -a STM32F405-olimex/STM32F405-olimex/Drivers/STM32F4xx_HAL_Driver stm32/STM32F4xx_HAL_Driver + cp -a STM32F405-olimex/STM32F405-olimex/Middlewares/ST/STM32_USB_Device_Library stm32/STM32_USB_Device_Library + cp -a STM32F405-olimex/STM32F405-olimex/Inc stm32/Inc + cp -a STM32F405-olimex/STM32F405-olimex/Src stm32/Src ADDED at91lib/boards/arduino_due_x/arduino_due_x.h Index: at91lib/boards/arduino_due_x/arduino_due_x.h ================================================================== --- at91lib/boards/arduino_due_x/arduino_due_x.h +++ at91lib/boards/arduino_due_x/arduino_due_x.h @@ -0,0 +1,797 @@ +/** + * \file + * + * \brief Arduino Due/X Board Definition. + * + * Copyright (c) 2011 - 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef ARDUINO_DUE_X_H_INCLUDED +#define ARDUINO_DUE_X_H_INCLUDED + +#include "compiler.h" +#include "system_sam3x.h" +#include "exceptions.h" + +/* ------------------------------------------------------------------------ */ + +/** + * \page arduino_due_x_opfreq "Arduino Due/X - Operating frequencies" + * This page lists several definition related to the board operating frequency + * + * \section Definitions + * - \ref BOARD_FREQ_* + * - \ref BOARD_MCK + */ + +/*! Board oscillator settings */ +#define BOARD_FREQ_SLCK_XTAL (32768U) +#define BOARD_FREQ_SLCK_BYPASS (32768U) +#define BOARD_FREQ_MAINCK_XTAL (12000000U) +#define BOARD_FREQ_MAINCK_BYPASS (12000000U) + +/*! Master clock frequency */ +#define BOARD_MCK CHIP_FREQ_CPU_MAX +#define BOARD_NO_32K_XTAL + +/** board main clock xtal statup time */ +#define BOARD_OSC_STARTUP_US 15625 + +/* ------------------------------------------------------------------------ */ + +/** + * \page arduino_due_x_board_info "Arduino Due/X - Board informations" + * This page lists several definition related to the board description. + * + * \section Definitions + * - \ref BOARD_NAME + */ + +/*! Name of the board */ +#define BOARD_NAME "Arduino Due/X" +/*! Board definition */ +#define arduinoduex +/*! Family definition (already defined) */ +#define sam3x +/*! Core definition */ +#define cortexm3 + +/* ------------------------------------------------------------------------ */ + +/** + * \page arduino_due_x_piodef "Arduino Due/X - PIO definitions" + * This pages lists all the pio definitions. The constants + * are named using the following convention: PIN_* for a constant which defines + * a single Pin instance (but may include several PIOs sharing the same + * controller), and PINS_* for a list of Pin instances. + * + */ + +/** + * \file + * ADC + * - \ref PIN_ADC0_AD1 + * - \ref PINS_ADC + * + */ + +/** + * \note ADC pins are automatically configured by the ADC peripheral as soon as + * the corresponding channel is enabled. + * + * \note On Arduino Due/X, Channel 1 is labelled A6 on the PCB. + */ + +/*! ADC_AD1 pin definition. */ +#define PIN_ADC0_AD1 {PIO_PA3X1_AD1, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT} +#define PINS_ADC_TRIG PIO_PA11_IDX +#define PINS_ADC_TRIG_FLAG (PIO_PERIPH_B | PIO_DEFAULT) +/*! Pins ADC */ +#define PINS_ADC PIN_ADC0_AD1 + +/** + * \file + * DAC + * + */ + +/** + * \note DAC pins are automatically configured by the DAC peripheral as soon + * as the corresponding channel is enabled. + * + * \note On Arduino Due/X, channel 0 is labelled A12 and channel 1 is labelled + * A13 on the PCB. + */ + + +/** + * \file + * LEDs + * + */ + +/* ------------------------------------------------------------------------ */ +/* LEDS */ +/* ------------------------------------------------------------------------ */ +/*! Power LED pin definition (ORANGE). L */ +#define PIN_POWER_LED {PIO_PB27, PIOB, ID_PIOB, PIO_OUTPUT_1, PIO_DEFAULT} +/*! LED #1 pin definition */ +#define PIN_USER_LED1 {PIO_PC21, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} +/*! LED #2 pin definition */ +#define PIN_USER_LED2 {PIO_PC22, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} +/*! LED #3 pin definition */ +#define PIN_USER_LED3 {PIO_PC23, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} + +/*! List of all LEDs definitions. */ +#define PINS_LEDS PIN_USER_LED1, PIN_USER_LED2, PIN_USER_LED3, PIN_POWER_LED + +/*! LED #0 "L" pin definition (ORANGE).*/ +#define LED_0_NAME "Orange_LED" +#define LED0_GPIO (PIO_PB27_IDX) +#define LED0_FLAGS (PIO_TYPE_PIO_OUTPUT_1 | PIO_DEFAULT) +#define LED0_ACTIVE_LEVEL 0 + +#define PIN_LED_0 {1 << 27, PIOB, ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT} +#define PIN_LED_0_MASK (1 << 27) +#define PIN_LED_0_PIO PIOB +#define PIN_LED_0_ID ID_PIOB +#define PIN_LED_0_TYPE PIO_OUTPUT_0 +#define PIN_LED_0_ATTR PIO_DEFAULT + +/*! LED #1 pin definition */ +#define LED_1_NAME "External_LED_on_PWM9_connector_output" +#define LED1_GPIO (PIO_PC21_IDX) +#define LED1_FLAGS (PIO_TYPE_PIO_OUTPUT_1 | PIO_DEFAULT) +#define LED1_ACTIVE_LEVEL 0 + +#define PIN_LED_1 {1 << 21, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} +#define PIN_LED_1_MASK (1 << 21) +#define PIN_LED_1_PIO PIOC +#define PIN_LED_1_ID ID_PIOC +#define PIN_LED_1_TYPE PIO_OUTPUT_1 +#define PIN_LED_1_ATTR PIO_DEFAULT + +/*! LED #2 pin detection */ +#define LED2_GPIO (PIO_PC22_IDX) +#define LED2_FLAGS (PIO_TYPE_PIO_OUTPUT_1 | PIO_DEFAULT) +#define LED2_ACTIVE_LEVEL 0 + +#define PIN_LED_2 {1 << 22, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} +#define PIN_LED_2_MASK (1 << 22) +#define PIN_LED_2_PIO PIOC +#define PIN_LED_2_ID ID_PIOC +#define PIN_LED_2_TYPE PIO_OUTPUT_1 +#define PIN_LED_2_ATTR PIO_DEFAULT + +/*! LED #3 pin detection */ +#define LED3_GPIO (PIO_PC23_IDX) +#define LED3_FLAGS (PIO_TYPE_PIO_OUTPUT_1 | PIO_DEFAULT) +#define LED3_ACTIVE_LEVEL 1 + +#define BOARD_NUM_OF_LED 4 +#define PIN_LED_3 {1 << 23, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} +#define PIN_LED_3_MASK (1 << 23) +#define PIN_LED_3_PIO PIOC +#define PIN_LED_3_ID ID_PIOC +#define PIN_LED_3_TYPE PIO_OUTPUT_1 +#define PIN_LED_3_ATTR PIO_DEFAULT + +/** + * \file + * Push buttons + * - \ref PIN_PB_LEFT_CLICK + * - \ref PIN_PB_RIGHT_CLICK + * - \ref PINS_PUSHBUTTONS + * - \ref PUSHBUTTON_BP1 + * - \ref PUSHBUTTON_BP2 + * + */ + +/* ------------------------------------------------------------------------ */ +/* PUSHBUTTONS */ +/* ------------------------------------------------------------------------ */ + +/**************************changing**********************************/ + +/** Push button LEFT CLICK definition. + * Attributes = pull-up + debounce + interrupt on falling edge. */ +#define PIN_PB_LEFT_CLICK {PIO_PD8, PIOD, ID_PIOD, PIO_INPUT,\ + PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_FALL_EDGE} + +/** Push button RIGHT CLICK definition. + * Attributes = pull-up + debounce + interrupt on falling edge. */ +#define PIN_PB_RIGHT_CLICK {PIO_PC28, PIOC, ID_PIOC, PIO_INPUT,\ + PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_FALL_EDGE} + +/*! List of all push button definitions. */ +#define PINS_PUSHBUTTONS PIN_PB_LEFT_CLICK, PIN_PB_RIGHT_CLICK + +/*! Push button #1 index. */ +#define PUSHBUTTON_BP1 0 +/*! Push button #2 index. */ +#define PUSHBUTTON_BP2 1 + +/*! Push button LEFT CLICK index. */ +#define PUSHBUTTON_LEFT 0 +/*! Push button RIGHT CLICK index. */ +#define PUSHBUTTON_RIGHT 1 + +/** Push button #0 definition. + * Attributes = pull-up + debounce + interrupt on rising edge. */ +#define PUSHBUTTON_1_NAME "External_PB1_on_PWM12_connector_output" + +#define GPIO_PUSH_BUTTON_1 (PIO_PD8_IDX) +#define GPIO_PUSH_BUTTON_1_FLAGS\ + (PIO_INPUT | PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE) + +#define PIN_PUSHBUTTON_1 {PIO_PD8, PIOD, ID_PIOD, PIO_INPUT,\ + PIO_PULLUP } +#define PIN_PUSHBUTTON_1_MASK PIO_PD8 +#define PIN_PUSHBUTTON_1_PIO PIOD +#define PIN_PUSHBUTTON_1_ID ID_PIOD +#define PIN_PUSHBUTTON_1_TYPE PIO_INPUT +#define PIN_PUSHBUTTON_1_ATTR (PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE) + +/** Push button #1 definition. + * Attributes = pull-up + debounce + interrupt on falling edge. */ +#define PUSHBUTTON_2_NAME "External_PB2_on_PWM3_connector_output" +#define GPIO_PUSH_BUTTON_2 (PIO_PC28_IDX) +#define GPIO_PUSH_BUTTON_2_FLAGS\ + (PIO_INPUT | PIO_PULLUP) + +#define PIN_PUSHBUTTON_2 {PIO_PC28, PIOC, ID_PIOC, PIO_INPUT,\ + PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_FALL_EDGE} +#define PIN_PUSHBUTTON_2_MASK PIO_PC28 +#define PIN_PUSHBUTTON_2_PIO PIOC +#define PIN_PUSHBUTTON_2_ID ID_PIOC +#define PIN_PUSHBUTTON_2_TYPE PIO_INPUT +#define PIN_PUSHBUTTON_2_ATTR (PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_FALL_EDGE) + + +#define PIN_TC0_TIOA1 (PIO_PA2_IDX) +#define PIN_TC0_TIOA1_MUX (IOPORT_MODE_MUX_A) +#define PIN_TC0_TIOA1_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) + +#define PIN_TC0_TIOA1_PIO PIOA +#define PIN_TC0_TIOA1_MASK PIO_PA2 +#define PIN_TC0_TIOA1_ID ID_PIOA +#define PIN_TC0_TIOA1_TYPE PIO_PERIPH_A +#define PIN_TC0_TIOA1_ATTR PIO_DEFAULT + + +#define PIN_TC0_TIOA0 (PIO_PB25_IDX) +#define PIN_TC0_TIOA0_MUX (IOPORT_MODE_MUX_B) +#define PIN_TC0_TIOA0_FLAGS (PIO_INPUT | PIO_DEFAULT) + +#define PIN_TC0_TIOA0_PIO PIOB +#define PIN_TC0_TIOA0_MASK PIO_PB25 +#define PIN_TC0_TIOA0_ID ID_PIOB +#define PIN_TC0_TIOA0_TYPE PIO_INPUT +#define PIN_TC0_TIOA0_ATTR PIO_DEFAULT + +/** + * \file + * PWMC + * - \ref PIN_PWMC_PWMH0 + * - \ref PIN_PWMC_PWML4 + * - \ref PIN_PWMC_PWML5 + * - \ref PIN_PWMC_PWML6 + * - \ref PIN_PWM_LED0 + * - \ref PIN_PWM_LED1 + * - \ref PIN_PWM_LED2 + * + */ + +/* ------------------------------------------------------------------------ */ +/* PWM */ +/* ------------------------------------------------------------------------ */ +/*! PWMC PWM0 TRIG pin definition: Output High. */ +#define PIN_PWMC_PWMH0_TRIG PIO_PB12_IDX +#define PIN_PWMC_PWMH0_TRIG_FLAG PIO_PERIPH_B | PIO_DEFAULT + +/*! PWMC PWM4 pin definition: Output Low. */ +#define PIN_PWMC_PWML4\ + {PIO_PC21B_PWML4, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} +/*! PWMC PWM5 pin definition: Output Low. */ +#define PIN_PWMC_PWML5\ + {PIO_PC22B_PWML5, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} +/*! PWMC PWM6 pin definition: Output High. */ +#define PIN_PWMC_PWML6\ + {PIO_PC23B_PWML6, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} + +/*! PWM pins definition for LED0 */ +#define PIN_PWM_LED0 PIN_PWMC_PWML4 +/*! PWM pins definition for LED1 */ +#define PIN_PWM_LED1 PIN_PWMC_PWML5 +/*! PWM pins definition for LED2 */ +#define PIN_PWM_LED2 PIN_PWMC_PWML6 + + +/*! PWM channel for LED0 */ +#define CHANNEL_PWM_LED0 PWM_CHANNEL_4 +/*! PWM channel for LED1 */ +#define CHANNEL_PWM_LED1 PWM_CHANNEL_5 +/*! PWM channel for LED2 */ +#define CHANNEL_PWM_LED2 PWM_CHANNEL_6 + +/*! PWM "PWM7" LED0 pin definitions.*/ +#define PIN_PWM_LED0_GPIO PIO_PC21_IDX +#define PIN_PWM_LED0_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) +#define PIN_PWM_LED0_CHANNEL PWM_CHANNEL_4 + +/*! PWM "PWM8" LED1 pin definitions.*/ +#define PIN_PWM_LED1_GPIO PIO_PC22_IDX +#define PIN_PWM_LED1_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) +#define PIN_PWM_LED1_CHANNEL PWM_CHANNEL_5 + +/*! PWM "PWM9" LED2 pin definitions.*/ +#define PIN_PWM_LED2_GPIO PIO_PC23_IDX +#define PIN_PWM_LED2_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) +#define PIN_PWM_LED2_CHANNEL PWM_CHANNEL_6 + +/** + * \file + * SPI + * + */ + +/* ------------------------------------------------------------------------ */ +/* SPI */ +/* ------------------------------------------------------------------------ */ +/*! SPI0 MISO pin definition. */ +#define SPI0_MISO_GPIO (PIO_PA25_IDX) +#define SPI0_MISO_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) +/*! SPI0 MOSI pin definition. */ +#define SPI0_MOSI_GPIO (PIO_PA26_IDX) +#define SPI0_MOSI_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) +/*! SPI0 SPCK pin definition. */ +#define SPI0_SPCK_GPIO (PIO_PA27_IDX) +#define SPI0_SPCK_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) + +/*! SPI0 chip select 0 pin definition. (Only one configuration is possible) */ +#define SPI0_NPCS0_GPIO (PIO_PA28_IDX) +#define SPI0_NPCS0_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) +/*! SPI0 chip select 1 pin definition. (multiple configurations are possible) */ +#define SPI0_NPCS1_PA29_GPIO (PIO_PA29_IDX) +#define SPI0_NPCS1_PA29_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) +#define SPI0_NPCS1_PB20_GPIO (PIO_PB20_IDX) +#define SPI0_NPCS1_PB20_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) +/*! SPI0 chip select 2 pin definition. (multiple configurations are possible) */ +#define SPI0_NPCS2_PA30_GPIO (PIO_PA30_IDX) +#define SPI0_NPCS2_PA30_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) +#define SPI0_NPCS2_PB21_GPIO (PIO_PB21_IDX) +#define SPI0_NPCS2_PB21_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) +/*! SPI0 chip select 3 pin definition. (multiple configurations are possible) */ +#define SPI0_NPCS3_PA31_GPIO (PIO_PA31_IDX) +#define SPI0_NPCS3_PA31_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) +#define SPI0_NPCS3_PB23_GPIO (PIO_PB23_IDX) +#define SPI0_NPCS3_PB23_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) + +/*! SPI1 MISO pin definition. */ +#define SPI1_MISO_GPIO (PIO_PE28_IDX) +#define SPI1_MISO_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) +/*! SPI1 MOSI pin definition. */ +#define SPI1_MOSI_GPIO (PIO_PE29_IDX) +#define SPI1_MOSI_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) +/*! SPI1 SPCK pin definition. */ +#define SPI1_SPCK_GPIO (PIO_PE30_IDX) +#define SPI1_SPCK_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) +/*! SPI1 chip select 0 pin definition. (Only one configuration is possible) */ +#define SPI1_NPCS0_GPIO (PIO_PE31_IDX) +#define SPI1_NPCS0_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) +/*! SPI1 chip select 1 pin definition. (Only one configuration is possible) */ +#define SPI1_NPCS1_GPIO (PIO_PF0_IDX) +#define SPI1_NPCS1_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) +/*! SPI1 chip select 2 pin definition. (Only one configuration is possible) */ +#define SPI1_NPCS2_GPIO (PIO_PF1_IDX) +#define SPI1_NPCS2_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) +/*! SPI1 chip select 3 pin definition. (Only one configuration is possible) */ +#define SPI1_NPCS3_GPIO (PIO_PF2_IDX) +#define SPI1_NPCS3_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) + +/** + * \file + * SSC + * - \ref PIN_SSC_TD + * - \ref PIN_SSC_TK + * - \ref PIN_SSC_TF + * - \ref PIN_SSC_RD + * - \ref PIN_SSC_RK + * - \ref PIN_SSC_RF + * + */ +/* ------------------------------------------------------------------------ */ +/* SSC */ +/* ------------------------------------------------------------------------ */ +/** SSC pin Transmitter Data (TD) */ +#define PIN_SSC_TD (PIO_PA16_IDX) +#define PIN_SSC_TD_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) +/** SSC pin Transmitter Clock (TK) */ +#define PIN_SSC_TK (PIO_PA14_IDX) +#define PIN_SSC_TK_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) +/** SSC pin Transmitter FrameSync (TF) */ +#define PIN_SSC_TF (PIO_PA15_IDX) +#define PIN_SSC_TF_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) +/** SSC pin Receiver Data (RD) */ +#define PIN_SSC_RD (PIO_PB18_IDX) +#define PIN_SSC_RD_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) +/** SSC pin Receiver Clock (RK) */ +#define PIN_SSC_RK (PIO_PB19_IDX) +#define PIN_SSC_RK_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) +/** SSC pin Receiver FrameSync (RF) */ +#define PIN_SSC_RF (PIO_PB17_IDX) +#define PIN_SSC_RF_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) + +/** + * \file + * PCK0 + * - \ref PIN_PCK0 + * + */ + +/* ------------------------------------------------------------------------ */ +/* PCK */ +/* ------------------------------------------------------------------------ */ +/*! PCK0 */ +#define PIN_PCK0 (PIO_PA1_IDX) +#define PIN_PCK0_MUX (IOPORT_MODE_MUX_B) +#define PIN_PCK0_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) + +#define PIN_PCK_0_MASK PIO_PA1 +#define PIN_PCK_0_PIO PIOA +#define PIN_PCK_0_ID ID_PIOA +#define PIN_PCK_0_TYPE PIO_PERIPH_B +#define PIN_PCK_0_ATTR PIO_DEFAULT +/** + * \file + * UART + * - \ref PINS_UART + * + */ + +/* ------------------------------------------------------------------------ */ +/* UART */ +/* ------------------------------------------------------------------------ */ +/*! UART pins (UTXD0 and URXD0) definitions, PA8,9. (labeled RX0->0 and TX0->1)*/ +#define PINS_UART (PIO_PA8A_URXD | PIO_PA9A_UTXD) +#define PINS_UART_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) + +#define PINS_UART_MASK (PIO_PA8A_URXD | PIO_PA9A_UTXD) +#define PINS_UART_PIO PIOA +#define PINS_UART_ID ID_PIOA +#define PINS_UART_TYPE PIO_PERIPH_A +#define PINS_UART_ATTR PIO_DEFAULT + +/** + * \file + * USART0 + * - \ref PIN_USART0_RXD + * - \ref PIN_USART0_TXD + */ +/* ------------------------------------------------------------------------ */ +/* USART0 */ +/* ------------------------------------------------------------------------ */ +/*! USART0 pin RX (labeled RX1 19)*/ +#define PIN_USART0_RXD\ + {PIO_PA10A_RXD0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_USART0_RXD_IDX (PIO_PA10_IDX) +#define PIN_USART0_RXD_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) + +/*! USART0 pin TX (labeled TX1 18) */ +#define PIN_USART0_TXD\ + {PIO_PA11A_TXD0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_USART0_TXD_IDX (PIO_PA11_IDX) +#define PIN_USART0_TXD_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) + +/** + * \file + * USART1 + * - \ref PIN_USART1_RXD + * - \ref PIN_USART1_TXD + */ +/* ------------------------------------------------------------------------ */ +/* USART1 */ +/* ------------------------------------------------------------------------ */ +/*! USART1 pin RX (labeled RX2 17) */ +#define PIN_USART1_RXD\ + {PIO_PA12A_RXD1, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_USART1_RXD_IDX (PIO_PA12_IDX) +#define PIN_USART1_RXD_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) +/*! USART1 pin TX (labeled TX2 16) */ +#define PIN_USART1_TXD\ + {PIO_PA13A_TXD1, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_USART1_TXD_IDX (PIO_PA13_IDX) +#define PIN_USART1_TXD_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) +/** + * \file + * USART3 + * - \ref PIN_USART3_RXD + * - \ref PIN_USART3_TXD + */ + +/* ------------------------------------------------------------------------ */ +/* USART3 */ +/* ------------------------------------------------------------------------ */ +/*! USART3 pin RX (labeled RX3 15) */ +#define PIN_USART3_RXD\ + {PIO_PD5B_RXD3, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} +#define PIN_USART3_RXD_IDX (PIO_PD5_IDX) +#define PIN_USART3_RXD_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) +/*! USART3 pin TX (labeled RX3 14) */ +#define PIN_USART3_TXD\ + {PIO_PD4B_TXD3, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} +#define PIN_USART3_TXD_IDX (PIO_PD4_IDX) +#define PIN_USART3_TXD_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) +/** + * \file + * USB + * - \ref PIN_USBOTG_VBOF + * - \ref PIN_USB_FAULT + * + */ + +/* ------------------------------------------------------------------------ */ +/* USB */ +/* ------------------------------------------------------------------------ */ +/*! USB OTG VBus On/Off: Bus Power Control Port. */ +#define PIN_UOTGHS_VBOF { PIO_PB10, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_PULLUP } +/*! USB OTG Identification: Mini Connector Identification Port. */ +#define PIN_UOTGHS_ID { PIO_PB11, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_PULLUP } + +/*! Multiplexed pin used for USB_ID: */ +#define USB_ID PIO_PB11_IDX +#define USB_ID_GPIO (PIO_PB11_IDX) +#define USB_ID_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) +/*! Multiplexed pin used for USB_VBOF: */ +#define USB_VBOF PIO_PB10_IDX +#define USB_VBOF_GPIO (PIO_PB10_IDX) +#define USB_VBOF_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) +/*! Active level of the USB_VBOF output pin. */ +#define USB_VBOF_ACTIVE_LEVEL LOW +/* ------------------------------------------------------------------------ */ +/** + * \file + * TWI + */ +/* ------------------------------------------------------------------------ */ +/* TWI */ +/* ------------------------------------------------------------------------ */ +/*! TWI0 pins definition */ +#define TWI0_DATA_GPIO PIO_PA17_IDX +#define TWI0_DATA_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) +#define TWI0_CLK_GPIO PIO_PA18_IDX +#define TWI0_CLK_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) + +/*! TWI1 pins definition */ +#define TWI1_DATA_GPIO PIO_PB12_IDX +#define TWI1_DATA_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) +#define TWI1_CLK_GPIO PIO_PB13_IDX +#define TWI1_CLK_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) + +/* ------------------------------------------------------------------------ */ +/** + * \file + * NMA7341 + * - \NMA7341L_CHANNEL + * - \PIN_NMA7341L + */ + + +/* ------------------------------------------------------------------------ */ +/** + * \file + * TouchScreen + * + * - \ref PIN_TSC_IRQ + * - \ref PIN_TSC_BUSY + * - \ref BOARD_TSC_SPI_BASE + * - \ref BOARD_TSC_SPI_ID + * - \ref BOARD_TSC_SPI_PINS + * - \ref BOARD_TSC_NPCS + * - \ref BOARD_TSC_NPCS_PIN + * + */ + +/* ------------------------------------------------------------------------ */ +/* Touchscreen */ +/* ------------------------------------------------------------------------ */ +/*! Touchscreen controller IRQ pin definition. */ +#define PIN_TSC_IRQ {PIO_PA31, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP} +/*! Touchscreen controller Busy pin definition. */ +#define PIN_TSC_BUSY {PIO_PA30, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP} + +/*! Chip select pin connected to the touchscreen controller. */ +/* We use PIO mode for chip select to meet ADS7843's timing specification */ +#define BOARD_TSC_NPCS_PIN\ + {PIO_PA28A_SPI0_NPCS0, PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_PULLUP} + +/** + * \file + * EMAC + * - BOARD_EMAC_PHY_ADDR: Phy MAC address + * - BOARD_EMAC_MODE_RMII: Enable RMII connection with the PHY + */ +/*! EMAC pins */ +#define PIN_EEMAC_EREFCK PIO_PB0_IDX +#define PIN_EMAC_ETXEN PIO_PB1_IDX +#define PIN_EMAC_ETX0 PIO_PB2_IDX +#define PIN_EMAC_ETX1 PIO_PB3_IDX +#define PIN_EMAC_ECRSDV PIO_PB4_IDX +#define PIN_EMAC_ERX0 PIO_PB5_IDX +#define PIN_EMAC_ERX1 PIO_PB6_IDX +#define PIN_EMAC_ERXER PIO_PB7_IDX +#define PIN_EMAC_EMDC PIO_PB8_IDX +#define PIN_EMAC_EMDIO PIO_PB9_IDX +#define PIN_EMAC_FLAGS PIO_PERIPH_A | PIO_DEFAULT + +/*! EMAC PHY address */ +#define BOARD_EMAC_PHY_ADDR 0 +/*! EMAC RMII mode */ +#define BOARD_EMAC_MODE_RMII 1 + +/* ------------------------------------------------------------------------ */ +/* NAND FLASH */ +/* ------------------------------------------------------------------------ */ +/* Chip select number for nand */ +#define BOARD_NAND_CS 0 + +/*! Address for transferring command bytes to the nandflash. */ +#define BOARD_NF_COMMAND_ADDR 0x60400000 +/*! Address for transferring address bytes to the nandflash. */ +#define BOARD_NF_ADDRESS_ADDR 0x60200000 +/*! Address for transferring data bytes to the nandflash. */ +#define BOARD_NF_DATA_ADDR 0x60000000 +/* Bus width for NAND */ +#define CONF_NF_BUSWIDTH 8 +/* SMC NFC using five address cycle */ +#define CONF_NF_NEED_FIVE_ADDRESS_CYCLES 1 +/* Access timing for NAND */ +#define CONF_NF_SETUP_TIMING (SMC_SETUP_NWE_SETUP(0) \ + | SMC_SETUP_NCS_WR_SETUP(0) \ + | SMC_SETUP_NRD_SETUP(0) \ + | SMC_SETUP_NCS_RD_SETUP(0)) +#define CONF_NF_PULSE_TIMING (SMC_PULSE_NWE_PULSE(2) \ + | SMC_PULSE_NCS_WR_PULSE(3) \ + | SMC_PULSE_NRD_PULSE(2) \ + | SMC_PULSE_NCS_RD_PULSE(3)) +#define CONF_NF_CYCLE_TIMING (SMC_CYCLE_NWE_CYCLE(3) \ + | SMC_CYCLE_NRD_CYCLE(3)) +#define CONF_NF_TIMING (SMC_TIMINGS_TCLR(1) \ + | SMC_TIMINGS_TADL(6) \ + | SMC_TIMINGS_TAR(4) \ + | SMC_TIMINGS_TRR(2) \ + | SMC_TIMINGS_TWB(9) \ + | SMC_TIMINGS_RBNSEL(7) \ + | (SMC_TIMINGS_NFSEL)) +/* Support DMA */ +#define CONF_NF_USE_DMA +#ifdef CONF_NF_USE_DMA +/* DMA channel used for NF */ +#define CONF_NF_DMA_CHANNEL 0 +#endif + +/* ------------------------------------------------------------------------ */ +/* SDRAM */ +/* ------------------------------------------------------------------------ */ +/*! Board SDRAM size for MT48LC16M16A2 */ +#define BOARD_SDRAM_SIZE (32 * 1024 * 1024) /* 32 MB */ + +/*! List of all SDRAM pins definitions */ +#define PIO_SDRAM_SDCKE PIO_PD13 +#define PIO_SDRAM_SDCS PIO_PD12 +#define PIO_SDRAM_RAS PIO_PD15 +#define PIO_SDRAM_CAS PIO_PD16 +#define PIO_SDRAM_BA0 PIO_PD6 +#define PIO_SDRAM_BA1 PIO_PD7 +#define PIO_SDRAM_SDWE PIO_PD14 +//#define PIO_SDRAM_NBS0 PIO_PC21 +#define PIO_SDRAM_NBS1 PIO_PD10 +#define PIO_SDRAM_DATA (0xffff << 2) /*PIO_PC2--PIO_PC17 */ +//#define PIO_SDRAM_SDA0_A7 (0xff << 23) /*PIO_PC23--PIO_PC30 */ +#define PIO_SDRAM_SDA8 PIO_PD22 +#define PIO_SDRAM_SDA9 PIO_PD23 +#define PIO_SDRAM_SDA11 PIO_PD25 +#define PIO_SDRAM_SDA12 PIO_PD4 +#define PIO_SDRAM_SDA10 PIO_PD11 + +/*! List of all SDRAM pins definitions */ +#define PINS_SDRAM_PIOC\ + { PIO_SDRAM_DATA | PIO_SDRAM_NBS0 | PIO_SDRAM_SDA0_A7,\ + PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP } + +#define PINS_SDRAM_PIOD\ + { PIO_SDRAM_SDCKE | PIO_SDRAM_SDCS |\ + PIO_SDRAM_RAS | PIO_SDRAM_CAS |\ + PIO_SDRAM_BA0 | PIO_SDRAM_BA1 |\ + PIO_SDRAM_SDWE | PIO_SDRAM_NBS1 |\ + PIO_SDRAM_SDA10 |\ + PIO_SDRAM_SDA8 | PIO_SDRAM_SDA9 |\ + PIO_SDRAM_SDA11 | PIO_SDRAM_SDA12,\ + PIOD, ID_PIOD, PIO_PERIPH_A, PIO_PULLUP } + +/* PIO18 is used as SDRAM Enable on EK-REVB board */ +#define PINS_SDRAM_EN\ + { (1 << 18), PIOD, ID_PIOD, PIO_OUTPUT_1, PIO_DEFAULT } + +#define PINS_SDRAM PINS_SDRAM_PIOC, PINS_SDRAM_PIOD, PINS_SDRAM_EN + +/*! SDRAM bus width */ +#define BOARD_SDRAM_BUSWIDTH 16 + +/* SDRAMC clock speed */ +#define SDRAMC_CLK (BOARD_MCK) + +/** + * \file + * \section NorFlash + * - \ref BOARD_NORFLASH_ADDR + * + */ + +/* ------------------------------------------------------------------------ */ +/* NOR FLASH */ +/* ------------------------------------------------------------------------ */ +/*! Address for transferring command bytes to the norflash. */ +#define BOARD_NORFLASH_ADDR 0x60000000 + +/*! TWI ID for EEPROM application to use */ +#define BOARD_ID_TWI_EEPROM ID_TWI0 +/*! TWI Base for TWI EEPROM application to use */ +#define BOARD_BASE_TWI_EEPROM TWI0 + +/*! USART RX pin for application */ +#define BOARD_PIN_USART_RXD PIN_USART0_RXD +/*! USART TX pin for application */ +#define BOARD_PIN_USART_TXD PIN_USART0_TXD +/*! USART Base for application */ +#define BOARD_USART_BASE USART0 +/*! USART ID for application */ +#define BOARD_ID_USART ID_USART0 +/*! USART1 Base for application */ +#define BOARD_USART1_BASE USART1 +/*! USART1 ID for application */ +#define BOARD_ID_USART1 ID_USART1 +/*! USART3 Base for application */ +#define BOARD_USART3_BASE USART3 +/*! USART3 ID for application */ +#define BOARD_ID_USART3 ID_USART3 + +#define CONSOLE_UART UART +#define CONSOLE_UART_ID ID_UART + +#endif /* ARDUINO_DUE_X_H_INCLUDED */ ADDED at91lib/boards/arduino_due_x/board_config/conf_board.h Index: at91lib/boards/arduino_due_x/board_config/conf_board.h ================================================================== --- at91lib/boards/arduino_due_x/board_config/conf_board.h +++ at91lib/boards/arduino_due_x/board_config/conf_board.h @@ -0,0 +1,98 @@ +/** + * \file + * + * \brief Arduino Due/X board configuration. + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef CONF_BOARD_H +#define CONF_BOARD_H + +/* Configure UART pins */ +#define CONF_BOARD_UART_CONSOLE + +/* Enable USB interface (USB) for host mode */ +#define CONF_BOARD_USB_PORT + +/* Configure ADC example pins */ +//#define CONF_BOARD_ADC + +/* Configure PWM LED0 pin */ +//#define CONF_BOARD_PWM_LED0 + +/* Configure PWM LED1 pin */ +//#define CONF_BOARD_PWM_LED1 + +/* Configure PWM LED2 pin */ +//#define CONF_BOARD_PWM_LED2 + +/* Configure SPI0 pins */ +//#define CONF_BOARD_SPI0 +//#define CONF_BOARD_SPI0_NPCS0 +//#define CONF_BOARD_SPI0_NPCS1 +//#define CONF_BOARD_SPI0_NPCS2 +//#define CONF_BOARD_SPI0_NPCS3 + +/* Configure SPI1 pins */ +//#define CONF_BOARD_SPI1 +//#define CONF_BOARD_SPI1_NPCS0 +//#define CONF_BOARD_SPI1_NPCS1 +//#define CONF_BOARD_SPI1_NPCS2 +//#define CONF_BOARD_SPI1_NPCS3 + +//#define CONF_BOARD_TWI0 + +//#define CONF_BOARD_TWI1 + +/* Configure USART RXD pin */ +//#define CONF_BOARD_USART_RXD + +/* Configure USART TXD pin */ +//#define CONF_BOARD_USART_TXD + +/* Configure USART CTS pin */ +//#define CONF_BOARD_USART_CTS + +/* Configure USART RTS pin */ +//#define CONF_BOARD_USART_RTS + +/* Configure USART synchronous communication SCK pin */ +//#define CONF_BOARD_USART_SCK + +#endif // CONF_BOARD_H ADDED at91lib/boards/arduino_due_x/debug_scripts/gcc/arduino_due_x_flash.gdb Index: at91lib/boards/arduino_due_x/debug_scripts/gcc/arduino_due_x_flash.gdb ================================================================== --- at91lib/boards/arduino_due_x/debug_scripts/gcc/arduino_due_x_flash.gdb +++ at91lib/boards/arduino_due_x/debug_scripts/gcc/arduino_due_x_flash.gdb @@ -0,0 +1,35 @@ +#******************************************************* +# +# Connect to J-Link and debug application in flash on SAM3X. +# + +# Define 'reset' command +define reset + +# Connect to the J-Link gdb server +target remote localhost:2331 + +# Reset the chip to get to a known state +monitor reset + +# Select flash device +monitor flash device = AT91SAM3X8E + +# Enable flash download and flash breakpoints +monitor flash download = 1 + +# Load the program +load + +# Reset peripheral (RSTC_CR) +set *0x400e1a00 = 0xA5000004 + +# Initialize PC and stack pointer +mon reg sp=(0x80000) +#set *0x80004 = *0x80004 & 0xFFFFFFFE +mon reg pc=(0x80004) + +info reg + +# End of 'reset' command +end ADDED at91lib/boards/arduino_due_x/debug_scripts/gcc/arduino_due_x_sram.gdb Index: at91lib/boards/arduino_due_x/debug_scripts/gcc/arduino_due_x_sram.gdb ================================================================== --- at91lib/boards/arduino_due_x/debug_scripts/gcc/arduino_due_x_sram.gdb +++ at91lib/boards/arduino_due_x/debug_scripts/gcc/arduino_due_x_sram.gdb @@ -0,0 +1,35 @@ +#******************************************************* +# +# Connect to J-Link and debug application in sram on SAM3X. +# + +# Define 'reset' command +define reset + +# Connect to the J-Link gdb server +target remote localhost:2331 + +# Reset the chip to get to a known state +monitor reset + +# Select flash device +monitor flash device = AT91SAM3X8E + +# Enable flash download and flash breakpoints +monitor flash download = 1 + +# Load the program +load + +# Reset peripheral (RSTC_CR) +set *0x400e1a00 = 0xA5000004 + +# Initialize PC and stack pointer +mon reg sp=(0x20000000) +#set *0x20000004 = *0x20000004 & 0xFFFFFFFE +mon reg pc=(0x20000004) + +info reg + +# End of 'reset' command +end ADDED at91lib/boards/arduino_due_x/init.c Index: at91lib/boards/arduino_due_x/init.c ================================================================== --- at91lib/boards/arduino_due_x/init.c +++ at91lib/boards/arduino_due_x/init.c @@ -0,0 +1,196 @@ +/** + * \file + * + * \brief Arduino Due/X board init. + * + * Copyright (c) 2011 - 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "compiler.h" +#include "board.h" +#include "conf_board.h" +#include "gpio/gpio.h" +#include "ioport/ioport.h" + +void board_init(void) +{ +#ifndef CONF_BOARD_KEEP_WATCHDOG_AT_INIT + /* Disable the watchdog */ + WDT->WDT_MR = WDT_MR_WDDIS; +#endif + + /* GPIO has been deprecated, the old code just keeps it for compatibility. + * In new designs IOPORT is used instead. + * Here IOPORT must be initialized for others to use before setting up IO. + */ + ioport_init(); + /* Configure LED pins */ + gpio_configure_pin(LED0_GPIO, LED0_FLAGS); + gpio_configure_pin(LED1_GPIO, LED1_FLAGS); + gpio_configure_pin(LED2_GPIO, LED2_FLAGS); + + /* Configure Push Button pins */ + gpio_configure_pin(GPIO_PUSH_BUTTON_1, GPIO_PUSH_BUTTON_1_FLAGS); + gpio_configure_pin(GPIO_PUSH_BUTTON_2, GPIO_PUSH_BUTTON_2_FLAGS); + +#ifdef CONF_BOARD_UART_CONSOLE + /* Configure UART pins */ + gpio_configure_group(PINS_UART_PIO, PINS_UART, PINS_UART_FLAGS); +#endif + + /* Configure ADC example pins */ +#ifdef CONF_BOARD_ADC + /* TC TIOA configuration */ + gpio_configure_pin(PIN_TC0_TIOA0,PIN_TC0_TIOA0_FLAGS); + + /* ADC Trigger configuration */ + gpio_configure_pin(PINS_ADC_TRIG, PINS_ADC_TRIG_FLAG); + + /* PWMH0 configuration */ + gpio_configure_pin(PIN_PWMC_PWMH0_TRIG, PIN_PWMC_PWMH0_TRIG_FLAG); +#endif + +#ifdef CONF_BOARD_PWM_LED0 + /* Configure PWM LED0 pin */ + gpio_configure_pin(PIN_PWM_LED0_GPIO, PIN_PWM_LED0_FLAGS); +#endif + +#ifdef CONF_BOARD_PWM_LED1 + /* Configure PWM LED1 pin */ + gpio_configure_pin(PIN_PWM_LED1_GPIO, PIN_PWM_LED1_FLAGS); +#endif + +#ifdef CONF_BOARD_PWM_LED2 + /* Configure PWM LED2 pin */ + gpio_configure_pin(PIN_PWM_LED2_GPIO, PIN_PWM_LED2_FLAGS); +#endif + + /* Configure SPI0 pins */ +#ifdef CONF_BOARD_SPI0 + gpio_configure_pin(SPI0_MISO_GPIO, SPI0_MISO_FLAGS); + gpio_configure_pin(SPI0_MOSI_GPIO, SPI0_MOSI_FLAGS); + gpio_configure_pin(SPI0_SPCK_GPIO, SPI0_SPCK_FLAGS); + + /** + * For NPCS 1, 2, and 3, different PINs can be used to access the same + * NPCS line. + * Depending on the application requirements, the default PIN may not be + * available. + * Hence a different PIN should be selected using the + * CONF_BOARD_SPI_NPCS_GPIO and + * CONF_BOARD_SPI_NPCS_FLAGS macros. + */ + +# ifdef CONF_BOARD_SPI0_NPCS0 + gpio_configure_pin(SPI0_NPCS0_GPIO, SPI0_NPCS0_FLAGS); +# endif + +# ifdef CONF_BOARD_SPI0_NPCS1 + gpio_configure_pin(SPI0_NPCS1_PA29_GPIO,SPI0_NPCS1_PA29_FLAGS); +# endif +#endif // #ifdef CONF_BOARD_SPI0 + + /* Configure SPI1 pins */ +#ifdef CONF_BOARD_SPI1 + gpio_configure_pin(SPI1_MISO_GPIO, SPI1_MISO_FLAGS); + gpio_configure_pin(SPI1_MOSI_GPIO, SPI1_MOSI_FLAGS); + gpio_configure_pin(SPI1_SPCK_GPIO, SPI1_SPCK_FLAGS); + +# ifdef CONF_BOARD_SPI1_NPCS0 + gpio_configure_pin(SPI1_NPCS0_GPIO, SPI1_NPCS0_FLAGS); +# endif + +# ifdef CONF_BOARD_SPI1_NPCS1 + gpio_configure_pin(SPI1_NPCS1_GPIO, SPI1_NPCS1_FLAGS); +# endif + +# ifdef CONF_BOARD_SPI1_NPCS2 + gpio_configure_pin(SPI1_NPCS2_GPIO, SPI1_NPCS2_FLAGS); +# endif + +# ifdef CONF_BOARD_SPI1_NPCS3 + gpio_configure_pin(SPI1_NPCS3_GPIO, SPI1_NPCS3_FLAGS); +# endif +#endif + +#ifdef CONF_BOARD_TWI0 + gpio_configure_pin(TWI0_DATA_GPIO, TWI0_DATA_FLAGS); + gpio_configure_pin(TWI0_CLK_GPIO, TWI0_CLK_FLAGS); +#endif + +#ifdef CONF_BOARD_TWI1 + gpio_configure_pin(TWI1_DATA_GPIO, TWI1_DATA_FLAGS); + gpio_configure_pin(TWI1_CLK_GPIO, TWI1_CLK_FLAGS); +#endif + +#ifdef CONF_BOARD_USART_RXD + /* Configure USART RXD pin */ + gpio_configure_pin(PIN_USART0_RXD_IDX, PIN_USART0_RXD_FLAGS); +#endif + +#ifdef CONF_BOARD_USART_TXD + /* Configure USART TXD pin */ + gpio_configure_pin(PIN_USART0_TXD_IDX, PIN_USART0_TXD_FLAGS); +#endif + +#ifdef CONF_BOARD_USB_PORT + /* Configure USB_ID (UOTGID) pin */ + gpio_configure_pin(USB_ID_GPIO, USB_ID_FLAGS); + /* Configure USB_VBOF (UOTGVBOF) pin */ + gpio_configure_pin(USB_VBOF_GPIO, USB_VBOF_FLAGS); +#endif + +#ifdef CONF_BOARD_MMA7341L + /* Configure MMA7341L mode set control pin */ + gpio_configure_pin(PIN_MMA7341L_MODE, PIN_MMA7341L_MODE_FLAG); + /* Configure MMA7341L x,y,z axis output voltage pin */ + gpio_configure_pin(PIN_MMA7341L_X_AXIS, PIN_MMA7341L_X_AXIS_FLAG); + gpio_configure_pin(PIN_MMA7341L_Y_AXIS, PIN_MMA7341L_Y_AXIS_FLAG); + gpio_configure_pin(PIN_MMA7341L_Z_AXIS, PIN_MMA7341L_Z_AXIS_FLAG); +#endif + +#ifdef CONF_BOARD_ADS7843 + /* Configure Touchscreen SPI pins */ + gpio_configure_pin(BOARD_ADS7843_IRQ_GPIO,BOARD_ADS7843_IRQ_FLAGS); + gpio_configure_pin(BOARD_ADS7843_BUSY_GPIO, BOARD_ADS7843_BUSY_FLAGS); + gpio_configure_pin(SPI0_MISO_GPIO, SPI0_MISO_FLAGS); + gpio_configure_pin(SPI0_MOSI_GPIO, SPI0_MOSI_FLAGS); + gpio_configure_pin(SPI0_SPCK_GPIO, SPI0_SPCK_FLAGS); + gpio_configure_pin(SPI0_NPCS0_GPIO, SPI0_NPCS0_FLAGS); +#endif +} ADDED at91lib/boards/arduino_due_x/led.c Index: at91lib/boards/arduino_due_x/led.c ================================================================== --- at91lib/boards/arduino_due_x/led.c +++ at91lib/boards/arduino_due_x/led.c @@ -0,0 +1,106 @@ +/** + * \file + * + * \brief Arduino Due/X LEDs support package. + * + * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "board.h" +#include "led.h" +#include "gpio.h" + +#define ACTIVE_LEVEL_IS_HIGH 1 + +typedef const struct +{ + uint32_t ul_port_id; //!< LED GPIO port. + uint32_t ul_active_level; //!< Active level of the LED. +} tLED_DESCRIPTOR; + +//! Hardware descriptors of all LEDs. +static tLED_DESCRIPTOR LED_DESCRIPTOR[BOARD_NUM_OF_LED] = +{ +#define INSERT_LED_DESCRIPTOR(LED_NO, unused) \ + { \ + LED##LED_NO##_GPIO, LED##LED_NO##_ACTIVE_LEVEL \ + }, + MREPEAT(BOARD_NUM_OF_LED, INSERT_LED_DESCRIPTOR, ~) +#undef INSERT_LED_DESCRIPTOR +}; + +/*! \brief Turns off the specified LEDs. + * + * \param led_gpio LED to turn off (LEDx_GPIO). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +void LED_Off(uint32_t led_gpio) +{ + uint32_t i; + for (i = 0; i < BOARD_NUM_OF_LED; i++) { + if (led_gpio == LED_DESCRIPTOR[i].ul_port_id) { + if (LED_DESCRIPTOR[i].ul_active_level == ACTIVE_LEVEL_IS_HIGH) { + gpio_set_pin_low(led_gpio); + } else { + gpio_set_pin_high(led_gpio); + } + } + } +} + +/*! \brief Turns on the specified LEDs. + * + * \param led_gpio LED to turn on (LEDx_GPIO). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +void LED_On(uint32_t led_gpio) +{ + uint32_t i; + for (i = 0; i < BOARD_NUM_OF_LED; i++) { + if (led_gpio == LED_DESCRIPTOR[i].ul_port_id) { + if (LED_DESCRIPTOR[i].ul_active_level == ACTIVE_LEVEL_IS_HIGH) { + gpio_set_pin_high(led_gpio); + } else { + gpio_set_pin_low(led_gpio); + } + } + } +} + ADDED at91lib/boards/arduino_due_x/led.h Index: at91lib/boards/arduino_due_x/led.h ================================================================== --- at91lib/boards/arduino_due_x/led.h +++ at91lib/boards/arduino_due_x/led.h @@ -0,0 +1,73 @@ +/** + * \file + * + * \brief Arduino Due/X LEDs support package. + * + * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _LED_H_ +#define _LED_H_ + +#include "gpio.h" + +/*! \brief Turns off the specified LEDs. + * + * \param led_gpio LED to turn off (LEDx_GPIO). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +void LED_Off(uint32_t led_gpio); + +/*! \brief Turns on the specified LEDs. + * + * \param led_gpio LED to turn on (LEDx_GPIO). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +void LED_On(uint32_t led_gpio); + +/*! \brief Toggles the specified LEDs. + * + * \param led_gpio LED to toggle (LEDx_GPIO). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +#define LED_Toggle(led_gpio) gpio_toggle_pin(led_gpio) + +#endif // _LED_H_ ADDED at91lib/boards/arduino_due_x/sam3x8e/flash.lds Index: at91lib/boards/arduino_due_x/sam3x8e/flash.lds ================================================================== --- at91lib/boards/arduino_due_x/sam3x8e/flash.lds +++ at91lib/boards/arduino_due_x/sam3x8e/flash.lds @@ -0,0 +1,157 @@ +/** + * \file + * + * \brief Flash Linker script for SAM. + * + * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00080000, LENGTH = 0x00080000 /* Flash, 512K */ + sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* sram0, 64K */ + sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00008000 /* sram1, 32K */ + ram (rwx) : ORIGIN = 0x20070000, LENGTH = 0x00018000 /* sram, 96K */ +/* ram (rwx) : ORIGIN = ORIGIN( sram1 )-LENGTH( sram0 ), LENGTH = LENGTH( sram0 )+LENGTH( sram1 ) */ /* sram, 96K */ +} + +/* The stack size used by the application. NOTE: you need to adjust */ +__stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 0x2000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + __stack_size__; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} ADDED at91lib/boards/arduino_due_x/sam3x8e/sram.lds Index: at91lib/boards/arduino_due_x/sam3x8e/sram.lds ================================================================== --- at91lib/boards/arduino_due_x/sam3x8e/sram.lds +++ at91lib/boards/arduino_due_x/sam3x8e/sram.lds @@ -0,0 +1,156 @@ +/** + * \file + * + * \brief SRAM Linker script for SAM. + * + * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00080000, LENGTH = 0x00080000 /* Flash, 512K */ + sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* sram0, 64K */ + sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00008000 /* sram1, 32K */ + ram (rwx) : ORIGIN = 0x20070000, LENGTH = 0x00018000 /* sram, 96K */ +/* ram (rwx) : ORIGIN = ORIGIN( sram1 )-LENGTH( sram0 ), LENGTH = LENGTH( sram0 )+LENGTH( sram1 ) */ /* sram, 96K */ +} + +/* The stack size used by the application. NOTE: you need to adjust */ +__stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 0x2000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + _sstack = .; + . = . + __stack_size__; + . = ALIGN(8); + _estack = .; + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _end = . ; +} Index: at91lib/boards/board.h ================================================================== --- at91lib/boards/board.h +++ at91lib/boards/board.h @@ -103,11 +103,10 @@ #define STK600_MEGA 39 //!< STK600 MEGA board. #define MEGA_1284P_XPLAINED 40 //!< ATmega1284P Xplained board. #define SAM4S_XPLAINED 41 //!< SAM4S Xplained board. #define ATXMEGA128A1_QT600 42 //!< QT600 ATXMEGA128A1 MCU board. #define ARDUINO_DUE_X 43 //!< Arduino Due/X board. -#define due 43 //!< Arduino Due/X board. #define STK600_RCUC3L3 44 //!< ATUCL3 STK600 board #define SAM4L_EK 45 //!< SAM4L-EK board. #define STK600_MEGA_RF 46 //!< STK600 MEGA RF EVK board. #define XMEGA_C3_XPLAINED 47 //!< ATxmega384C3 Xplained board. #define STK600_RC032X 48 //!< STK600 with RC032X routing card board. @@ -124,11 +123,10 @@ #define SAMD20_XPLAINED_PRO 59 //!< SAMD20 Xplained PRO board #define SAM4L8_XPLAINED_PRO 60 //!< SAM4L8 Xplained Pro board. #define SAM4N_XPLAINED_PRO 61 //!< SAM4N-XPLAINED-PRO board. #define XMEGA_A3_REB_CBB 62 //!< SAM4L8 Xplained Pro board. #define ATMEGARFX_RCB 63 //!< RFR2 & RFA1 RCB -#define K4PI 96 //!< 4pi #define SIMULATOR_XMEGA_A1 97 //!< Simulator for XMEGA A1 devices #define AVR_SIMULATOR_UC3 98 //!< AVR SIMULATOR for AVR UC3 device family. #define USER_BOARD 99 //!< User-reserved board (if any). #define DUMMY_BOARD 100 //!< Dummy board to support board-independent applications (e.g. bootloader) //! @} @@ -232,12 +230,12 @@ #elif BOARD == SAM4S_EK2 # include "sam4s_ek2/sam4s_ek2.h" # include "system_sam4s.h" #elif BOARD == MEGA_1284P_XPLAINED /*No header-file to include*/ -#elif (BOARD == ARDUINO_DUE_X) -# include "due/arduino_due_x.h" +#elif BOARD == ARDUINO_DUE_X +# include "arduino_due_x/arduino_due_x.h" # include "system_sam3x.h" #elif BOARD == SAM4L_EK # include "sam4l_ek/sam4l_ek.h" #elif BOARD == SAM4E_EK # include "sam4e_ek/sam4e_ek.h" DELETED at91lib/boards/due/arduino_due_x.h Index: at91lib/boards/due/arduino_due_x.h ================================================================== --- at91lib/boards/due/arduino_due_x.h +++ at91lib/boards/due/arduino_due_x.h @@ -1,797 +0,0 @@ -/** - * \file - * - * \brief Arduino Due/X Board Definition. - * - * Copyright (c) 2011 - 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef ARDUINO_DUE_X_H_INCLUDED -#define ARDUINO_DUE_X_H_INCLUDED - -#include "compiler.h" -#include "system_sam3x.h" -#include "exceptions.h" - -/* ------------------------------------------------------------------------ */ - -/** - * \page arduino_due_x_opfreq "Arduino Due/X - Operating frequencies" - * This page lists several definition related to the board operating frequency - * - * \section Definitions - * - \ref BOARD_FREQ_* - * - \ref BOARD_MCK - */ - -/*! Board oscillator settings */ -#define BOARD_FREQ_SLCK_XTAL (32768U) -#define BOARD_FREQ_SLCK_BYPASS (32768U) -#define BOARD_FREQ_MAINCK_XTAL (12000000U) -#define BOARD_FREQ_MAINCK_BYPASS (12000000U) - -/*! Master clock frequency */ -#define BOARD_MCK CHIP_FREQ_CPU_MAX -#define BOARD_NO_32K_XTAL - -/** board main clock xtal statup time */ -#define BOARD_OSC_STARTUP_US 15625 - -/* ------------------------------------------------------------------------ */ - -/** - * \page arduino_due_x_board_info "Arduino Due/X - Board informations" - * This page lists several definition related to the board description. - * - * \section Definitions - * - \ref BOARD_NAME - */ - -/*! Name of the board */ -#define BOARD_NAME "Arduino Due/X" -/*! Board definition */ -#define arduinoduex -/*! Family definition (already defined) */ -#define sam3x -/*! Core definition */ -#define cortexm3 - -/* ------------------------------------------------------------------------ */ - -/** - * \page arduino_due_x_piodef "Arduino Due/X - PIO definitions" - * This pages lists all the pio definitions. The constants - * are named using the following convention: PIN_* for a constant which defines - * a single Pin instance (but may include several PIOs sharing the same - * controller), and PINS_* for a list of Pin instances. - * - */ - -/** - * \file - * ADC - * - \ref PIN_ADC0_AD1 - * - \ref PINS_ADC - * - */ - -/** - * \note ADC pins are automatically configured by the ADC peripheral as soon as - * the corresponding channel is enabled. - * - * \note On Arduino Due/X, Channel 1 is labelled A6 on the PCB. - */ - -/*! ADC_AD1 pin definition. */ -#define PIN_ADC0_AD1 {PIO_PA3X1_AD1, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT} -#define PINS_ADC_TRIG PIO_PA11_IDX -#define PINS_ADC_TRIG_FLAG (PIO_PERIPH_B | PIO_DEFAULT) -/*! Pins ADC */ -#define PINS_ADC PIN_ADC0_AD1 - -/** - * \file - * DAC - * - */ - -/** - * \note DAC pins are automatically configured by the DAC peripheral as soon - * as the corresponding channel is enabled. - * - * \note On Arduino Due/X, channel 0 is labelled A12 and channel 1 is labelled - * A13 on the PCB. - */ - - -/** - * \file - * LEDs - * - */ - -/* ------------------------------------------------------------------------ */ -/* LEDS */ -/* ------------------------------------------------------------------------ */ -/*! Power LED pin definition (ORANGE). L */ -#define PIN_POWER_LED {PIO_PB27, PIOB, ID_PIOB, PIO_OUTPUT_1, PIO_DEFAULT} -/*! LED #1 pin definition */ -#define PIN_USER_LED1 {PIO_PC21, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} -/*! LED #2 pin definition */ -#define PIN_USER_LED2 {PIO_PC22, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} -/*! LED #3 pin definition */ -#define PIN_USER_LED3 {PIO_PC23, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} - -/*! List of all LEDs definitions. */ -#define PINS_LEDS PIN_USER_LED1, PIN_USER_LED2, PIN_USER_LED3, PIN_POWER_LED - -/*! LED #0 "L" pin definition (ORANGE).*/ -#define LED_0_NAME "Orange_LED" -#define LED0_GPIO (PIO_PB27_IDX) -#define LED0_FLAGS (PIO_TYPE_PIO_OUTPUT_1 | PIO_DEFAULT) -#define LED0_ACTIVE_LEVEL 0 - -#define PIN_LED_0 {1 << 27, PIOB, ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT} -#define PIN_LED_0_MASK (1 << 27) -#define PIN_LED_0_PIO PIOB -#define PIN_LED_0_ID ID_PIOB -#define PIN_LED_0_TYPE PIO_OUTPUT_0 -#define PIN_LED_0_ATTR PIO_DEFAULT - -/*! LED #1 pin definition */ -#define LED_1_NAME "External_LED_on_PWM9_connector_output" -#define LED1_GPIO (PIO_PC21_IDX) -#define LED1_FLAGS (PIO_TYPE_PIO_OUTPUT_1 | PIO_DEFAULT) -#define LED1_ACTIVE_LEVEL 0 - -#define PIN_LED_1 {1 << 21, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} -#define PIN_LED_1_MASK (1 << 21) -#define PIN_LED_1_PIO PIOC -#define PIN_LED_1_ID ID_PIOC -#define PIN_LED_1_TYPE PIO_OUTPUT_1 -#define PIN_LED_1_ATTR PIO_DEFAULT - -/*! LED #2 pin detection */ -#define LED2_GPIO (PIO_PC22_IDX) -#define LED2_FLAGS (PIO_TYPE_PIO_OUTPUT_1 | PIO_DEFAULT) -#define LED2_ACTIVE_LEVEL 0 - -#define PIN_LED_2 {1 << 22, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} -#define PIN_LED_2_MASK (1 << 22) -#define PIN_LED_2_PIO PIOC -#define PIN_LED_2_ID ID_PIOC -#define PIN_LED_2_TYPE PIO_OUTPUT_1 -#define PIN_LED_2_ATTR PIO_DEFAULT - -/*! LED #3 pin detection */ -#define LED3_GPIO (PIO_PC23_IDX) -#define LED3_FLAGS (PIO_TYPE_PIO_OUTPUT_1 | PIO_DEFAULT) -#define LED3_ACTIVE_LEVEL 1 - -#define BOARD_NUM_OF_LED 4 -#define PIN_LED_3 {1 << 23, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} -#define PIN_LED_3_MASK (1 << 23) -#define PIN_LED_3_PIO PIOC -#define PIN_LED_3_ID ID_PIOC -#define PIN_LED_3_TYPE PIO_OUTPUT_1 -#define PIN_LED_3_ATTR PIO_DEFAULT - -/** - * \file - * Push buttons - * - \ref PIN_PB_LEFT_CLICK - * - \ref PIN_PB_RIGHT_CLICK - * - \ref PINS_PUSHBUTTONS - * - \ref PUSHBUTTON_BP1 - * - \ref PUSHBUTTON_BP2 - * - */ - -/* ------------------------------------------------------------------------ */ -/* PUSHBUTTONS */ -/* ------------------------------------------------------------------------ */ - -/**************************changing**********************************/ - -/** Push button LEFT CLICK definition. - * Attributes = pull-up + debounce + interrupt on falling edge. */ -#define PIN_PB_LEFT_CLICK {PIO_PD8, PIOD, ID_PIOD, PIO_INPUT,\ - PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_FALL_EDGE} - -/** Push button RIGHT CLICK definition. - * Attributes = pull-up + debounce + interrupt on falling edge. */ -#define PIN_PB_RIGHT_CLICK {PIO_PC28, PIOC, ID_PIOC, PIO_INPUT,\ - PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_FALL_EDGE} - -/*! List of all push button definitions. */ -#define PINS_PUSHBUTTONS PIN_PB_LEFT_CLICK, PIN_PB_RIGHT_CLICK - -/*! Push button #1 index. */ -#define PUSHBUTTON_BP1 0 -/*! Push button #2 index. */ -#define PUSHBUTTON_BP2 1 - -/*! Push button LEFT CLICK index. */ -#define PUSHBUTTON_LEFT 0 -/*! Push button RIGHT CLICK index. */ -#define PUSHBUTTON_RIGHT 1 - -/** Push button #0 definition. - * Attributes = pull-up + debounce + interrupt on rising edge. */ -#define PUSHBUTTON_1_NAME "External_PB1_on_PWM12_connector_output" - -#define GPIO_PUSH_BUTTON_1 (PIO_PD8_IDX) -#define GPIO_PUSH_BUTTON_1_FLAGS\ - (PIO_INPUT | PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE) - -#define PIN_PUSHBUTTON_1 {PIO_PD8, PIOD, ID_PIOD, PIO_INPUT,\ - PIO_PULLUP } -#define PIN_PUSHBUTTON_1_MASK PIO_PD8 -#define PIN_PUSHBUTTON_1_PIO PIOD -#define PIN_PUSHBUTTON_1_ID ID_PIOD -#define PIN_PUSHBUTTON_1_TYPE PIO_INPUT -#define PIN_PUSHBUTTON_1_ATTR (PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE) - -/** Push button #1 definition. - * Attributes = pull-up + debounce + interrupt on falling edge. */ -#define PUSHBUTTON_2_NAME "External_PB2_on_PWM3_connector_output" -#define GPIO_PUSH_BUTTON_2 (PIO_PC28_IDX) -#define GPIO_PUSH_BUTTON_2_FLAGS\ - (PIO_INPUT | PIO_PULLUP) - -#define PIN_PUSHBUTTON_2 {PIO_PC28, PIOC, ID_PIOC, PIO_INPUT,\ - PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_FALL_EDGE} -#define PIN_PUSHBUTTON_2_MASK PIO_PC28 -#define PIN_PUSHBUTTON_2_PIO PIOC -#define PIN_PUSHBUTTON_2_ID ID_PIOC -#define PIN_PUSHBUTTON_2_TYPE PIO_INPUT -#define PIN_PUSHBUTTON_2_ATTR (PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_FALL_EDGE) - - -#define PIN_TC0_TIOA1 (PIO_PA2_IDX) -#define PIN_TC0_TIOA1_MUX (IOPORT_MODE_MUX_A) -#define PIN_TC0_TIOA1_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) - -#define PIN_TC0_TIOA1_PIO PIOA -#define PIN_TC0_TIOA1_MASK PIO_PA2 -#define PIN_TC0_TIOA1_ID ID_PIOA -#define PIN_TC0_TIOA1_TYPE PIO_PERIPH_A -#define PIN_TC0_TIOA1_ATTR PIO_DEFAULT - - -#define PIN_TC0_TIOA0 (PIO_PB25_IDX) -#define PIN_TC0_TIOA0_MUX (IOPORT_MODE_MUX_B) -#define PIN_TC0_TIOA0_FLAGS (PIO_INPUT | PIO_DEFAULT) - -#define PIN_TC0_TIOA0_PIO PIOB -#define PIN_TC0_TIOA0_MASK PIO_PB25 -#define PIN_TC0_TIOA0_ID ID_PIOB -#define PIN_TC0_TIOA0_TYPE PIO_INPUT -#define PIN_TC0_TIOA0_ATTR PIO_DEFAULT - -/** - * \file - * PWMC - * - \ref PIN_PWMC_PWMH0 - * - \ref PIN_PWMC_PWML4 - * - \ref PIN_PWMC_PWML5 - * - \ref PIN_PWMC_PWML6 - * - \ref PIN_PWM_LED0 - * - \ref PIN_PWM_LED1 - * - \ref PIN_PWM_LED2 - * - */ - -/* ------------------------------------------------------------------------ */ -/* PWM */ -/* ------------------------------------------------------------------------ */ -/*! PWMC PWM0 TRIG pin definition: Output High. */ -#define PIN_PWMC_PWMH0_TRIG PIO_PB12_IDX -#define PIN_PWMC_PWMH0_TRIG_FLAG PIO_PERIPH_B | PIO_DEFAULT - -/*! PWMC PWM4 pin definition: Output Low. */ -#define PIN_PWMC_PWML4\ - {PIO_PC21B_PWML4, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} -/*! PWMC PWM5 pin definition: Output Low. */ -#define PIN_PWMC_PWML5\ - {PIO_PC22B_PWML5, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} -/*! PWMC PWM6 pin definition: Output High. */ -#define PIN_PWMC_PWML6\ - {PIO_PC23B_PWML6, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} - -/*! PWM pins definition for LED0 */ -#define PIN_PWM_LED0 PIN_PWMC_PWML4 -/*! PWM pins definition for LED1 */ -#define PIN_PWM_LED1 PIN_PWMC_PWML5 -/*! PWM pins definition for LED2 */ -#define PIN_PWM_LED2 PIN_PWMC_PWML6 - - -/*! PWM channel for LED0 */ -#define CHANNEL_PWM_LED0 PWM_CHANNEL_4 -/*! PWM channel for LED1 */ -#define CHANNEL_PWM_LED1 PWM_CHANNEL_5 -/*! PWM channel for LED2 */ -#define CHANNEL_PWM_LED2 PWM_CHANNEL_6 - -/*! PWM "PWM7" LED0 pin definitions.*/ -#define PIN_PWM_LED0_GPIO PIO_PC21_IDX -#define PIN_PWM_LED0_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) -#define PIN_PWM_LED0_CHANNEL PWM_CHANNEL_4 - -/*! PWM "PWM8" LED1 pin definitions.*/ -#define PIN_PWM_LED1_GPIO PIO_PC22_IDX -#define PIN_PWM_LED1_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) -#define PIN_PWM_LED1_CHANNEL PWM_CHANNEL_5 - -/*! PWM "PWM9" LED2 pin definitions.*/ -#define PIN_PWM_LED2_GPIO PIO_PC23_IDX -#define PIN_PWM_LED2_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) -#define PIN_PWM_LED2_CHANNEL PWM_CHANNEL_6 - -/** - * \file - * SPI - * - */ - -/* ------------------------------------------------------------------------ */ -/* SPI */ -/* ------------------------------------------------------------------------ */ -/*! SPI0 MISO pin definition. */ -#define SPI0_MISO_GPIO (PIO_PA25_IDX) -#define SPI0_MISO_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) -/*! SPI0 MOSI pin definition. */ -#define SPI0_MOSI_GPIO (PIO_PA26_IDX) -#define SPI0_MOSI_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) -/*! SPI0 SPCK pin definition. */ -#define SPI0_SPCK_GPIO (PIO_PA27_IDX) -#define SPI0_SPCK_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) - -/*! SPI0 chip select 0 pin definition. (Only one configuration is possible) */ -#define SPI0_NPCS0_GPIO (PIO_PA28_IDX) -#define SPI0_NPCS0_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) -/*! SPI0 chip select 1 pin definition. (multiple configurations are possible) */ -#define SPI0_NPCS1_PA29_GPIO (PIO_PA29_IDX) -#define SPI0_NPCS1_PA29_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) -#define SPI0_NPCS1_PB20_GPIO (PIO_PB20_IDX) -#define SPI0_NPCS1_PB20_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) -/*! SPI0 chip select 2 pin definition. (multiple configurations are possible) */ -#define SPI0_NPCS2_PA30_GPIO (PIO_PA30_IDX) -#define SPI0_NPCS2_PA30_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) -#define SPI0_NPCS2_PB21_GPIO (PIO_PB21_IDX) -#define SPI0_NPCS2_PB21_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) -/*! SPI0 chip select 3 pin definition. (multiple configurations are possible) */ -#define SPI0_NPCS3_PA31_GPIO (PIO_PA31_IDX) -#define SPI0_NPCS3_PA31_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) -#define SPI0_NPCS3_PB23_GPIO (PIO_PB23_IDX) -#define SPI0_NPCS3_PB23_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) - -/*! SPI1 MISO pin definition. */ -#define SPI1_MISO_GPIO (PIO_PE28_IDX) -#define SPI1_MISO_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) -/*! SPI1 MOSI pin definition. */ -#define SPI1_MOSI_GPIO (PIO_PE29_IDX) -#define SPI1_MOSI_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) -/*! SPI1 SPCK pin definition. */ -#define SPI1_SPCK_GPIO (PIO_PE30_IDX) -#define SPI1_SPCK_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) -/*! SPI1 chip select 0 pin definition. (Only one configuration is possible) */ -#define SPI1_NPCS0_GPIO (PIO_PE31_IDX) -#define SPI1_NPCS0_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) -/*! SPI1 chip select 1 pin definition. (Only one configuration is possible) */ -#define SPI1_NPCS1_GPIO (PIO_PF0_IDX) -#define SPI1_NPCS1_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) -/*! SPI1 chip select 2 pin definition. (Only one configuration is possible) */ -#define SPI1_NPCS2_GPIO (PIO_PF1_IDX) -#define SPI1_NPCS2_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) -/*! SPI1 chip select 3 pin definition. (Only one configuration is possible) */ -#define SPI1_NPCS3_GPIO (PIO_PF2_IDX) -#define SPI1_NPCS3_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) - -/** - * \file - * SSC - * - \ref PIN_SSC_TD - * - \ref PIN_SSC_TK - * - \ref PIN_SSC_TF - * - \ref PIN_SSC_RD - * - \ref PIN_SSC_RK - * - \ref PIN_SSC_RF - * - */ -/* ------------------------------------------------------------------------ */ -/* SSC */ -/* ------------------------------------------------------------------------ */ -/** SSC pin Transmitter Data (TD) */ -#define PIN_SSC_TD (PIO_PA16_IDX) -#define PIN_SSC_TD_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) -/** SSC pin Transmitter Clock (TK) */ -#define PIN_SSC_TK (PIO_PA14_IDX) -#define PIN_SSC_TK_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) -/** SSC pin Transmitter FrameSync (TF) */ -#define PIN_SSC_TF (PIO_PA15_IDX) -#define PIN_SSC_TF_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) -/** SSC pin Receiver Data (RD) */ -#define PIN_SSC_RD (PIO_PB18_IDX) -#define PIN_SSC_RD_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) -/** SSC pin Receiver Clock (RK) */ -#define PIN_SSC_RK (PIO_PB19_IDX) -#define PIN_SSC_RK_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) -/** SSC pin Receiver FrameSync (RF) */ -#define PIN_SSC_RF (PIO_PB17_IDX) -#define PIN_SSC_RF_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) - -/** - * \file - * PCK0 - * - \ref PIN_PCK0 - * - */ - -/* ------------------------------------------------------------------------ */ -/* PCK */ -/* ------------------------------------------------------------------------ */ -/*! PCK0 */ -#define PIN_PCK0 (PIO_PA1_IDX) -#define PIN_PCK0_MUX (IOPORT_MODE_MUX_B) -#define PIN_PCK0_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) - -#define PIN_PCK_0_MASK PIO_PA1 -#define PIN_PCK_0_PIO PIOA -#define PIN_PCK_0_ID ID_PIOA -#define PIN_PCK_0_TYPE PIO_PERIPH_B -#define PIN_PCK_0_ATTR PIO_DEFAULT -/** - * \file - * UART - * - \ref PINS_UART - * - */ - -/* ------------------------------------------------------------------------ */ -/* UART */ -/* ------------------------------------------------------------------------ */ -/*! UART pins (UTXD0 and URXD0) definitions, PA8,9. (labeled RX0->0 and TX0->1)*/ -#define PINS_UART (PIO_PA8A_URXD | PIO_PA9A_UTXD) -#define PINS_UART_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) - -#define PINS_UART_MASK (PIO_PA8A_URXD | PIO_PA9A_UTXD) -#define PINS_UART_PIO PIOA -#define PINS_UART_ID ID_PIOA -#define PINS_UART_TYPE PIO_PERIPH_A -#define PINS_UART_ATTR PIO_DEFAULT - -/** - * \file - * USART0 - * - \ref PIN_USART0_RXD - * - \ref PIN_USART0_TXD - */ -/* ------------------------------------------------------------------------ */ -/* USART0 */ -/* ------------------------------------------------------------------------ */ -/*! USART0 pin RX (labeled RX1 19)*/ -#define PIN_USART0_RXD\ - {PIO_PA10A_RXD0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_USART0_RXD_IDX (PIO_PA10_IDX) -#define PIN_USART0_RXD_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) - -/*! USART0 pin TX (labeled TX1 18) */ -#define PIN_USART0_TXD\ - {PIO_PA11A_TXD0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_USART0_TXD_IDX (PIO_PA11_IDX) -#define PIN_USART0_TXD_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) - -/** - * \file - * USART1 - * - \ref PIN_USART1_RXD - * - \ref PIN_USART1_TXD - */ -/* ------------------------------------------------------------------------ */ -/* USART1 */ -/* ------------------------------------------------------------------------ */ -/*! USART1 pin RX (labeled RX2 17) */ -#define PIN_USART1_RXD\ - {PIO_PA12A_RXD1, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_USART1_RXD_IDX (PIO_PA12_IDX) -#define PIN_USART1_RXD_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) -/*! USART1 pin TX (labeled TX2 16) */ -#define PIN_USART1_TXD\ - {PIO_PA13A_TXD1, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_USART1_TXD_IDX (PIO_PA13_IDX) -#define PIN_USART1_TXD_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) -/** - * \file - * USART3 - * - \ref PIN_USART3_RXD - * - \ref PIN_USART3_TXD - */ - -/* ------------------------------------------------------------------------ */ -/* USART3 */ -/* ------------------------------------------------------------------------ */ -/*! USART3 pin RX (labeled RX3 15) */ -#define PIN_USART3_RXD\ - {PIO_PD5B_RXD3, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} -#define PIN_USART3_RXD_IDX (PIO_PD5_IDX) -#define PIN_USART3_RXD_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) -/*! USART3 pin TX (labeled RX3 14) */ -#define PIN_USART3_TXD\ - {PIO_PD4B_TXD3, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} -#define PIN_USART3_TXD_IDX (PIO_PD4_IDX) -#define PIN_USART3_TXD_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) -/** - * \file - * USB - * - \ref PIN_USBOTG_VBOF - * - \ref PIN_USB_FAULT - * - */ - -/* ------------------------------------------------------------------------ */ -/* USB */ -/* ------------------------------------------------------------------------ */ -/*! USB OTG VBus On/Off: Bus Power Control Port. */ -#define PIN_UOTGHS_VBOF { PIO_PB10, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_PULLUP } -/*! USB OTG Identification: Mini Connector Identification Port. */ -#define PIN_UOTGHS_ID { PIO_PB11, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_PULLUP } - -/*! Multiplexed pin used for USB_ID: */ -#define USB_ID PIO_PB11_IDX -#define USB_ID_GPIO (PIO_PB11_IDX) -#define USB_ID_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) -/*! Multiplexed pin used for USB_VBOF: */ -#define USB_VBOF PIO_PB10_IDX -#define USB_VBOF_GPIO (PIO_PB10_IDX) -#define USB_VBOF_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) -/*! Active level of the USB_VBOF output pin. */ -#define USB_VBOF_ACTIVE_LEVEL LOW -/* ------------------------------------------------------------------------ */ -/** - * \file - * TWI - */ -/* ------------------------------------------------------------------------ */ -/* TWI */ -/* ------------------------------------------------------------------------ */ -/*! TWI0 pins definition */ -#define TWI0_DATA_GPIO PIO_PA17_IDX -#define TWI0_DATA_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) -#define TWI0_CLK_GPIO PIO_PA18_IDX -#define TWI0_CLK_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) - -/*! TWI1 pins definition */ -#define TWI1_DATA_GPIO PIO_PB12_IDX -#define TWI1_DATA_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) -#define TWI1_CLK_GPIO PIO_PB13_IDX -#define TWI1_CLK_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) - -/* ------------------------------------------------------------------------ */ -/** - * \file - * NMA7341 - * - \NMA7341L_CHANNEL - * - \PIN_NMA7341L - */ - - -/* ------------------------------------------------------------------------ */ -/** - * \file - * TouchScreen - * - * - \ref PIN_TSC_IRQ - * - \ref PIN_TSC_BUSY - * - \ref BOARD_TSC_SPI_BASE - * - \ref BOARD_TSC_SPI_ID - * - \ref BOARD_TSC_SPI_PINS - * - \ref BOARD_TSC_NPCS - * - \ref BOARD_TSC_NPCS_PIN - * - */ - -/* ------------------------------------------------------------------------ */ -/* Touchscreen */ -/* ------------------------------------------------------------------------ */ -/*! Touchscreen controller IRQ pin definition. */ -#define PIN_TSC_IRQ {PIO_PA31, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP} -/*! Touchscreen controller Busy pin definition. */ -#define PIN_TSC_BUSY {PIO_PA30, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP} - -/*! Chip select pin connected to the touchscreen controller. */ -/* We use PIO mode for chip select to meet ADS7843's timing specification */ -#define BOARD_TSC_NPCS_PIN\ - {PIO_PA28A_SPI0_NPCS0, PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_PULLUP} - -/** - * \file - * EMAC - * - BOARD_EMAC_PHY_ADDR: Phy MAC address - * - BOARD_EMAC_MODE_RMII: Enable RMII connection with the PHY - */ -/*! EMAC pins */ -#define PIN_EEMAC_EREFCK PIO_PB0_IDX -#define PIN_EMAC_ETXEN PIO_PB1_IDX -#define PIN_EMAC_ETX0 PIO_PB2_IDX -#define PIN_EMAC_ETX1 PIO_PB3_IDX -#define PIN_EMAC_ECRSDV PIO_PB4_IDX -#define PIN_EMAC_ERX0 PIO_PB5_IDX -#define PIN_EMAC_ERX1 PIO_PB6_IDX -#define PIN_EMAC_ERXER PIO_PB7_IDX -#define PIN_EMAC_EMDC PIO_PB8_IDX -#define PIN_EMAC_EMDIO PIO_PB9_IDX -#define PIN_EMAC_FLAGS PIO_PERIPH_A | PIO_DEFAULT - -/*! EMAC PHY address */ -#define BOARD_EMAC_PHY_ADDR 0 -/*! EMAC RMII mode */ -#define BOARD_EMAC_MODE_RMII 1 - -/* ------------------------------------------------------------------------ */ -/* NAND FLASH */ -/* ------------------------------------------------------------------------ */ -/* Chip select number for nand */ -#define BOARD_NAND_CS 0 - -/*! Address for transferring command bytes to the nandflash. */ -#define BOARD_NF_COMMAND_ADDR 0x60400000 -/*! Address for transferring address bytes to the nandflash. */ -#define BOARD_NF_ADDRESS_ADDR 0x60200000 -/*! Address for transferring data bytes to the nandflash. */ -#define BOARD_NF_DATA_ADDR 0x60000000 -/* Bus width for NAND */ -#define CONF_NF_BUSWIDTH 8 -/* SMC NFC using five address cycle */ -#define CONF_NF_NEED_FIVE_ADDRESS_CYCLES 1 -/* Access timing for NAND */ -#define CONF_NF_SETUP_TIMING (SMC_SETUP_NWE_SETUP(0) \ - | SMC_SETUP_NCS_WR_SETUP(0) \ - | SMC_SETUP_NRD_SETUP(0) \ - | SMC_SETUP_NCS_RD_SETUP(0)) -#define CONF_NF_PULSE_TIMING (SMC_PULSE_NWE_PULSE(2) \ - | SMC_PULSE_NCS_WR_PULSE(3) \ - | SMC_PULSE_NRD_PULSE(2) \ - | SMC_PULSE_NCS_RD_PULSE(3)) -#define CONF_NF_CYCLE_TIMING (SMC_CYCLE_NWE_CYCLE(3) \ - | SMC_CYCLE_NRD_CYCLE(3)) -#define CONF_NF_TIMING (SMC_TIMINGS_TCLR(1) \ - | SMC_TIMINGS_TADL(6) \ - | SMC_TIMINGS_TAR(4) \ - | SMC_TIMINGS_TRR(2) \ - | SMC_TIMINGS_TWB(9) \ - | SMC_TIMINGS_RBNSEL(7) \ - | (SMC_TIMINGS_NFSEL)) -/* Support DMA */ -#define CONF_NF_USE_DMA -#ifdef CONF_NF_USE_DMA -/* DMA channel used for NF */ -#define CONF_NF_DMA_CHANNEL 0 -#endif - -/* ------------------------------------------------------------------------ */ -/* SDRAM */ -/* ------------------------------------------------------------------------ */ -/*! Board SDRAM size for MT48LC16M16A2 */ -#define BOARD_SDRAM_SIZE (32 * 1024 * 1024) /* 32 MB */ - -/*! List of all SDRAM pins definitions */ -#define PIO_SDRAM_SDCKE PIO_PD13 -#define PIO_SDRAM_SDCS PIO_PD12 -#define PIO_SDRAM_RAS PIO_PD15 -#define PIO_SDRAM_CAS PIO_PD16 -#define PIO_SDRAM_BA0 PIO_PD6 -#define PIO_SDRAM_BA1 PIO_PD7 -#define PIO_SDRAM_SDWE PIO_PD14 -//#define PIO_SDRAM_NBS0 PIO_PC21 -#define PIO_SDRAM_NBS1 PIO_PD10 -#define PIO_SDRAM_DATA (0xffff << 2) /*PIO_PC2--PIO_PC17 */ -//#define PIO_SDRAM_SDA0_A7 (0xff << 23) /*PIO_PC23--PIO_PC30 */ -#define PIO_SDRAM_SDA8 PIO_PD22 -#define PIO_SDRAM_SDA9 PIO_PD23 -#define PIO_SDRAM_SDA11 PIO_PD25 -#define PIO_SDRAM_SDA12 PIO_PD4 -#define PIO_SDRAM_SDA10 PIO_PD11 - -/*! List of all SDRAM pins definitions */ -#define PINS_SDRAM_PIOC\ - { PIO_SDRAM_DATA | PIO_SDRAM_NBS0 | PIO_SDRAM_SDA0_A7,\ - PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP } - -#define PINS_SDRAM_PIOD\ - { PIO_SDRAM_SDCKE | PIO_SDRAM_SDCS |\ - PIO_SDRAM_RAS | PIO_SDRAM_CAS |\ - PIO_SDRAM_BA0 | PIO_SDRAM_BA1 |\ - PIO_SDRAM_SDWE | PIO_SDRAM_NBS1 |\ - PIO_SDRAM_SDA10 |\ - PIO_SDRAM_SDA8 | PIO_SDRAM_SDA9 |\ - PIO_SDRAM_SDA11 | PIO_SDRAM_SDA12,\ - PIOD, ID_PIOD, PIO_PERIPH_A, PIO_PULLUP } - -/* PIO18 is used as SDRAM Enable on EK-REVB board */ -#define PINS_SDRAM_EN\ - { (1 << 18), PIOD, ID_PIOD, PIO_OUTPUT_1, PIO_DEFAULT } - -#define PINS_SDRAM PINS_SDRAM_PIOC, PINS_SDRAM_PIOD, PINS_SDRAM_EN - -/*! SDRAM bus width */ -#define BOARD_SDRAM_BUSWIDTH 16 - -/* SDRAMC clock speed */ -#define SDRAMC_CLK (BOARD_MCK) - -/** - * \file - * \section NorFlash - * - \ref BOARD_NORFLASH_ADDR - * - */ - -/* ------------------------------------------------------------------------ */ -/* NOR FLASH */ -/* ------------------------------------------------------------------------ */ -/*! Address for transferring command bytes to the norflash. */ -#define BOARD_NORFLASH_ADDR 0x60000000 - -/*! TWI ID for EEPROM application to use */ -#define BOARD_ID_TWI_EEPROM ID_TWI0 -/*! TWI Base for TWI EEPROM application to use */ -#define BOARD_BASE_TWI_EEPROM TWI0 - -/*! USART RX pin for application */ -#define BOARD_PIN_USART_RXD PIN_USART0_RXD -/*! USART TX pin for application */ -#define BOARD_PIN_USART_TXD PIN_USART0_TXD -/*! USART Base for application */ -#define BOARD_USART_BASE USART0 -/*! USART ID for application */ -#define BOARD_ID_USART ID_USART0 -/*! USART1 Base for application */ -#define BOARD_USART1_BASE USART1 -/*! USART1 ID for application */ -#define BOARD_ID_USART1 ID_USART1 -/*! USART3 Base for application */ -#define BOARD_USART3_BASE USART3 -/*! USART3 ID for application */ -#define BOARD_ID_USART3 ID_USART3 - -#define CONSOLE_UART UART -#define CONSOLE_UART_ID ID_UART - -#endif /* ARDUINO_DUE_X_H_INCLUDED */ DELETED at91lib/boards/due/board_config/conf_board.h Index: at91lib/boards/due/board_config/conf_board.h ================================================================== --- at91lib/boards/due/board_config/conf_board.h +++ at91lib/boards/due/board_config/conf_board.h @@ -1,98 +0,0 @@ -/** - * \file - * - * \brief Arduino Due/X board configuration. - * - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef CONF_BOARD_H -#define CONF_BOARD_H - -/* Configure UART pins */ -#define CONF_BOARD_UART_CONSOLE - -/* Enable USB interface (USB) for host mode */ -#define CONF_BOARD_USB_PORT - -/* Configure ADC example pins */ -//#define CONF_BOARD_ADC - -/* Configure PWM LED0 pin */ -//#define CONF_BOARD_PWM_LED0 - -/* Configure PWM LED1 pin */ -//#define CONF_BOARD_PWM_LED1 - -/* Configure PWM LED2 pin */ -//#define CONF_BOARD_PWM_LED2 - -/* Configure SPI0 pins */ -//#define CONF_BOARD_SPI0 -//#define CONF_BOARD_SPI0_NPCS0 -//#define CONF_BOARD_SPI0_NPCS1 -//#define CONF_BOARD_SPI0_NPCS2 -//#define CONF_BOARD_SPI0_NPCS3 - -/* Configure SPI1 pins */ -//#define CONF_BOARD_SPI1 -//#define CONF_BOARD_SPI1_NPCS0 -//#define CONF_BOARD_SPI1_NPCS1 -//#define CONF_BOARD_SPI1_NPCS2 -//#define CONF_BOARD_SPI1_NPCS3 - -//#define CONF_BOARD_TWI0 - -//#define CONF_BOARD_TWI1 - -/* Configure USART RXD pin */ -//#define CONF_BOARD_USART_RXD - -/* Configure USART TXD pin */ -//#define CONF_BOARD_USART_TXD - -/* Configure USART CTS pin */ -//#define CONF_BOARD_USART_CTS - -/* Configure USART RTS pin */ -//#define CONF_BOARD_USART_RTS - -/* Configure USART synchronous communication SCK pin */ -//#define CONF_BOARD_USART_SCK - -#endif // CONF_BOARD_H DELETED at91lib/boards/due/conf_clock.h Index: at91lib/boards/due/conf_clock.h ================================================================== --- at91lib/boards/due/conf_clock.h +++ at91lib/boards/due/conf_clock.h @@ -1,97 +0,0 @@ -/** - * \file - * - * \brief SAM3X clock configuration. - * - * Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef CONF_CLOCK_H_INCLUDED -#define CONF_CLOCK_H_INCLUDED - -// ===== System Clock (MCK) Source Options -//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_RC -//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_XTAL -//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_BYPASS -//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_4M_RC -//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_8M_RC -//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_12M_RC -//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_XTAL -//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_BYPASS -#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK -//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_UPLLCK - -// ===== System Clock (MCK) Prescaler Options (Fmck = Fsys / (SYSCLK_PRES)) -//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_1 -#define CONFIG_SYSCLK_PRES SYSCLK_PRES_2 -//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_4 -//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_8 -//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_16 -//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_32 -//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_64 -//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_3 - -// ===== PLL0 (A) Options (Fpll = (Fclk * PLL_mul) / PLL_div) -// Use mul and div effective values here. -#define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL -#define CONFIG_PLL0_MUL 14 -#define CONFIG_PLL0_DIV 1 - -// ===== UPLL (UTMI) Hardware fixed at 480 MHz. - -// ===== USB Clock Source Options (Fusb = FpllX / USB_div) -// Use div effective value here. -//#define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL0 -#define CONFIG_USBCLK_SOURCE USBCLK_SRC_UPLL -#define CONFIG_USBCLK_DIV 1 - -// ===== Target frequency (System clock) -// - XTAL frequency: 12MHz -// - System clock source: PLLA -// - System clock prescaler: 2 (divided by 2) -// - PLLA source: XTAL -// - PLLA output: XTAL * 14 / 1 -// - System clock is: 12 * 14 / 1 /2 = 84MHz -// ===== Target frequency (USB Clock) -// - USB clock source: UPLL -// - USB clock divider: 1 (not divided) -// - UPLL frequency: 480MHz -// - USB clock: 480 / 1 = 480MHz - - -#endif /* CONF_CLOCK_H_INCLUDED */ DELETED at91lib/boards/due/conf_uart_serial.h Index: at91lib/boards/due/conf_uart_serial.h ================================================================== --- at91lib/boards/due/conf_uart_serial.h +++ at91lib/boards/due/conf_uart_serial.h @@ -1,54 +0,0 @@ -/** - * \file - * - * \brief Serial USART service configuration. - * - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef CONF_USART_SERIAL_H -#define CONF_USART_SERIAL_H - -/** UART Interface */ -#define CONF_UART CONSOLE_UART -/** Baudrate setting */ -#define CONF_UART_BAUDRATE 115200 -/** Parity setting */ -#define CONF_UART_PARITY UART_MR_PAR_NO - -#endif/* CONF_USART_SERIAL_H_INCLUDED */ DELETED at91lib/boards/due/init.c Index: at91lib/boards/due/init.c ================================================================== --- at91lib/boards/due/init.c +++ at91lib/boards/due/init.c @@ -1,196 +0,0 @@ -/** - * \file - * - * \brief Arduino Due/X board init. - * - * Copyright (c) 2011 - 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "compiler.h" -#include "board.h" -#include "conf_board.h" -#include "gpio/gpio.h" -#include "ioport/ioport.h" - -void board_init(void) -{ -#ifndef CONF_BOARD_KEEP_WATCHDOG_AT_INIT - /* Disable the watchdog */ - WDT->WDT_MR = WDT_MR_WDDIS; -#endif - - /* GPIO has been deprecated, the old code just keeps it for compatibility. - * In new designs IOPORT is used instead. - * Here IOPORT must be initialized for others to use before setting up IO. - */ - ioport_init(); - /* Configure LED pins */ - gpio_configure_pin(LED0_GPIO, LED0_FLAGS); - gpio_configure_pin(LED1_GPIO, LED1_FLAGS); - gpio_configure_pin(LED2_GPIO, LED2_FLAGS); - - /* Configure Push Button pins */ - gpio_configure_pin(GPIO_PUSH_BUTTON_1, GPIO_PUSH_BUTTON_1_FLAGS); - gpio_configure_pin(GPIO_PUSH_BUTTON_2, GPIO_PUSH_BUTTON_2_FLAGS); - -#ifdef CONF_BOARD_UART_CONSOLE - /* Configure UART pins */ - gpio_configure_group(PINS_UART_PIO, PINS_UART, PINS_UART_FLAGS); -#endif - - /* Configure ADC example pins */ -#ifdef CONF_BOARD_ADC - /* TC TIOA configuration */ - gpio_configure_pin(PIN_TC0_TIOA0,PIN_TC0_TIOA0_FLAGS); - - /* ADC Trigger configuration */ - gpio_configure_pin(PINS_ADC_TRIG, PINS_ADC_TRIG_FLAG); - - /* PWMH0 configuration */ - gpio_configure_pin(PIN_PWMC_PWMH0_TRIG, PIN_PWMC_PWMH0_TRIG_FLAG); -#endif - -#ifdef CONF_BOARD_PWM_LED0 - /* Configure PWM LED0 pin */ - gpio_configure_pin(PIN_PWM_LED0_GPIO, PIN_PWM_LED0_FLAGS); -#endif - -#ifdef CONF_BOARD_PWM_LED1 - /* Configure PWM LED1 pin */ - gpio_configure_pin(PIN_PWM_LED1_GPIO, PIN_PWM_LED1_FLAGS); -#endif - -#ifdef CONF_BOARD_PWM_LED2 - /* Configure PWM LED2 pin */ - gpio_configure_pin(PIN_PWM_LED2_GPIO, PIN_PWM_LED2_FLAGS); -#endif - - /* Configure SPI0 pins */ -#ifdef CONF_BOARD_SPI0 - gpio_configure_pin(SPI0_MISO_GPIO, SPI0_MISO_FLAGS); - gpio_configure_pin(SPI0_MOSI_GPIO, SPI0_MOSI_FLAGS); - gpio_configure_pin(SPI0_SPCK_GPIO, SPI0_SPCK_FLAGS); - - /** - * For NPCS 1, 2, and 3, different PINs can be used to access the same - * NPCS line. - * Depending on the application requirements, the default PIN may not be - * available. - * Hence a different PIN should be selected using the - * CONF_BOARD_SPI_NPCS_GPIO and - * CONF_BOARD_SPI_NPCS_FLAGS macros. - */ - -# ifdef CONF_BOARD_SPI0_NPCS0 - gpio_configure_pin(SPI0_NPCS0_GPIO, SPI0_NPCS0_FLAGS); -# endif - -# ifdef CONF_BOARD_SPI0_NPCS1 - gpio_configure_pin(SPI0_NPCS1_PA29_GPIO,SPI0_NPCS1_PA29_FLAGS); -# endif -#endif // #ifdef CONF_BOARD_SPI0 - - /* Configure SPI1 pins */ -#ifdef CONF_BOARD_SPI1 - gpio_configure_pin(SPI1_MISO_GPIO, SPI1_MISO_FLAGS); - gpio_configure_pin(SPI1_MOSI_GPIO, SPI1_MOSI_FLAGS); - gpio_configure_pin(SPI1_SPCK_GPIO, SPI1_SPCK_FLAGS); - -# ifdef CONF_BOARD_SPI1_NPCS0 - gpio_configure_pin(SPI1_NPCS0_GPIO, SPI1_NPCS0_FLAGS); -# endif - -# ifdef CONF_BOARD_SPI1_NPCS1 - gpio_configure_pin(SPI1_NPCS1_GPIO, SPI1_NPCS1_FLAGS); -# endif - -# ifdef CONF_BOARD_SPI1_NPCS2 - gpio_configure_pin(SPI1_NPCS2_GPIO, SPI1_NPCS2_FLAGS); -# endif - -# ifdef CONF_BOARD_SPI1_NPCS3 - gpio_configure_pin(SPI1_NPCS3_GPIO, SPI1_NPCS3_FLAGS); -# endif -#endif - -#ifdef CONF_BOARD_TWI0 - gpio_configure_pin(TWI0_DATA_GPIO, TWI0_DATA_FLAGS); - gpio_configure_pin(TWI0_CLK_GPIO, TWI0_CLK_FLAGS); -#endif - -#ifdef CONF_BOARD_TWI1 - gpio_configure_pin(TWI1_DATA_GPIO, TWI1_DATA_FLAGS); - gpio_configure_pin(TWI1_CLK_GPIO, TWI1_CLK_FLAGS); -#endif - -#ifdef CONF_BOARD_USART_RXD - /* Configure USART RXD pin */ - gpio_configure_pin(PIN_USART0_RXD_IDX, PIN_USART0_RXD_FLAGS); -#endif - -#ifdef CONF_BOARD_USART_TXD - /* Configure USART TXD pin */ - gpio_configure_pin(PIN_USART0_TXD_IDX, PIN_USART0_TXD_FLAGS); -#endif - -#ifdef CONF_BOARD_USB_PORT - /* Configure USB_ID (UOTGID) pin */ - gpio_configure_pin(USB_ID_GPIO, USB_ID_FLAGS); - /* Configure USB_VBOF (UOTGVBOF) pin */ - gpio_configure_pin(USB_VBOF_GPIO, USB_VBOF_FLAGS); -#endif - -#ifdef CONF_BOARD_MMA7341L - /* Configure MMA7341L mode set control pin */ - gpio_configure_pin(PIN_MMA7341L_MODE, PIN_MMA7341L_MODE_FLAG); - /* Configure MMA7341L x,y,z axis output voltage pin */ - gpio_configure_pin(PIN_MMA7341L_X_AXIS, PIN_MMA7341L_X_AXIS_FLAG); - gpio_configure_pin(PIN_MMA7341L_Y_AXIS, PIN_MMA7341L_Y_AXIS_FLAG); - gpio_configure_pin(PIN_MMA7341L_Z_AXIS, PIN_MMA7341L_Z_AXIS_FLAG); -#endif - -#ifdef CONF_BOARD_ADS7843 - /* Configure Touchscreen SPI pins */ - gpio_configure_pin(BOARD_ADS7843_IRQ_GPIO,BOARD_ADS7843_IRQ_FLAGS); - gpio_configure_pin(BOARD_ADS7843_BUSY_GPIO, BOARD_ADS7843_BUSY_FLAGS); - gpio_configure_pin(SPI0_MISO_GPIO, SPI0_MISO_FLAGS); - gpio_configure_pin(SPI0_MOSI_GPIO, SPI0_MOSI_FLAGS); - gpio_configure_pin(SPI0_SPCK_GPIO, SPI0_SPCK_FLAGS); - gpio_configure_pin(SPI0_NPCS0_GPIO, SPI0_NPCS0_FLAGS); -#endif -} DELETED at91lib/boards/due/sam3x8e/flash.lds Index: at91lib/boards/due/sam3x8e/flash.lds ================================================================== --- at91lib/boards/due/sam3x8e/flash.lds +++ at91lib/boards/due/sam3x8e/flash.lds @@ -1,157 +0,0 @@ -/** - * \file - * - * \brief Flash Linker script for SAM. - * - * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -SEARCH_DIR(.) - -/* Memory Spaces Definitions */ -MEMORY -{ - rom (rx) : ORIGIN = 0x00080000, LENGTH = 0x00080000 /* Flash, 512K */ - sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* sram0, 64K */ - sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00008000 /* sram1, 32K */ - ram (rwx) : ORIGIN = 0x20070000, LENGTH = 0x00018000 /* sram, 96K */ -/* ram (rwx) : ORIGIN = ORIGIN( sram1 )-LENGTH( sram0 ), LENGTH = LENGTH( sram0 )+LENGTH( sram1 ) */ /* sram, 96K */ -} - -/* The stack size used by the application. NOTE: you need to adjust */ -__stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 0x2000; - -/* Section Definitions */ -SECTIONS -{ - .text : - { - . = ALIGN(4); - _sfixed = .; - KEEP(*(.vectors .vectors.*)) - *(.text .text.* .gnu.linkonce.t.*) - *(.glue_7t) *(.glue_7) - *(.rodata .rodata* .gnu.linkonce.r.*) - *(.ARM.extab* .gnu.linkonce.armextab.*) - - /* Support C constructors, and C destructors in both user code - and the C library. This also provides support for C++ code. */ - . = ALIGN(4); - KEEP(*(.init)) - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(0x4); - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - - . = ALIGN(4); - _efixed = .; /* End of text section */ - } > rom - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - PROVIDE_HIDDEN (__exidx_start = .); - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > rom - PROVIDE_HIDDEN (__exidx_end = .); - - . = ALIGN(4); - _etext = .; - - .relocate : AT (_etext) - { - . = ALIGN(4); - _srelocate = .; - *(.ramfunc .ramfunc.*); - *(.data .data.*); - . = ALIGN(4); - _erelocate = .; - } > ram - - /* .bss section which is used for uninitialized data */ - .bss (NOLOAD) : - { - . = ALIGN(4); - _sbss = . ; - _szero = .; - *(.bss .bss.*) - *(COMMON) - . = ALIGN(4); - _ebss = . ; - _ezero = .; - } > ram - - /* stack section */ - .stack (NOLOAD): - { - . = ALIGN(8); - _sstack = .; - . = . + __stack_size__; - . = ALIGN(8); - _estack = .; - } > ram - - . = ALIGN(4); - _end = . ; -} DELETED at91lib/boards/due/sam3x8e/sram.lds Index: at91lib/boards/due/sam3x8e/sram.lds ================================================================== --- at91lib/boards/due/sam3x8e/sram.lds +++ at91lib/boards/due/sam3x8e/sram.lds @@ -1,156 +0,0 @@ -/** - * \file - * - * \brief SRAM Linker script for SAM. - * - * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -SEARCH_DIR(.) - -/* Memory Spaces Definitions */ -MEMORY -{ - rom (rx) : ORIGIN = 0x00080000, LENGTH = 0x00080000 /* Flash, 512K */ - sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* sram0, 64K */ - sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00008000 /* sram1, 32K */ - ram (rwx) : ORIGIN = 0x20070000, LENGTH = 0x00018000 /* sram, 96K */ -/* ram (rwx) : ORIGIN = ORIGIN( sram1 )-LENGTH( sram0 ), LENGTH = LENGTH( sram0 )+LENGTH( sram1 ) */ /* sram, 96K */ -} - -/* The stack size used by the application. NOTE: you need to adjust */ -__stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 0x2000; - -/* Section Definitions */ -SECTIONS -{ - .text : - { - . = ALIGN(4); - _sfixed = .; - KEEP(*(.vectors .vectors.*)) - *(.text .text.* .gnu.linkonce.t.*) - *(.glue_7t) *(.glue_7) - *(.rodata .rodata* .gnu.linkonce.r.*) - *(.ARM.extab* .gnu.linkonce.armextab.*) - - /* Support C constructors, and C destructors in both user code - and the C library. This also provides support for C++ code. */ - . = ALIGN(4); - KEEP(*(.init)) - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(0x4); - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - - . = ALIGN(4); - _efixed = .; /* End of text section */ - } > ram - - . = ALIGN(4); - _etext = .; - - .relocate : AT (_etext) - { - . = ALIGN(4); - _srelocate = .; - *(.ramfunc .ramfunc.*); - *(.data .data.*); - . = ALIGN(4); - _erelocate = .; - } > ram - - /* .bss section which is used for uninitialized data */ - .bss (NOLOAD) : - { - . = ALIGN(4); - _sbss = . ; - _szero = .; - *(.bss .bss.*) - *(COMMON) - . = ALIGN(4); - _ebss = . ; - _ezero = .; - } > ram - - /* stack section */ - .stack (NOLOAD): - { - _sstack = .; - . = . + __stack_size__; - . = ALIGN(8); - _estack = .; - } > ram - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - PROVIDE_HIDDEN (__exidx_start = .); - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > ram - PROVIDE_HIDDEN (__exidx_end = .); - - . = ALIGN(4); - _end = . ; -} Index: at91lib/peripherals/sleepmgr/sam/module_config/conf_sleepmgr.h ================================================================== --- at91lib/peripherals/sleepmgr/sam/module_config/conf_sleepmgr.h +++ at91lib/peripherals/sleepmgr/sam/module_config/conf_sleepmgr.h @@ -1,11 +1,11 @@ /** * \file * * \brief Chip-specific sleep manager configuration * - * Copyright (c) 2012-2013 Atmel Corporation. All rights reserved. + * Copyright (c) 2012 Atmel Corporation. All rights reserved. * * \asf_license_start * * \page License * Index: at91lib/peripherals/sleepmgr/sam/sleepmgr.c ================================================================== --- at91lib/peripherals/sleepmgr/sam/sleepmgr.c +++ at91lib/peripherals/sleepmgr/sam/sleepmgr.c @@ -1,11 +1,11 @@ /** * \file * * \brief SAM3/SAM4 Sleep manager implementation. * - * Copyright (c) 2012-2013 Atmel Corporation. All rights reserved. + * Copyright (c) 2012 Atmel Corporation. All rights reserved. * * \asf_license_start * * \page License * Index: at91lib/peripherals/sleepmgr/sam/sleepmgr.h ================================================================== --- at91lib/peripherals/sleepmgr/sam/sleepmgr.h +++ at91lib/peripherals/sleepmgr/sam/sleepmgr.h @@ -55,22 +55,11 @@ /** * \weakgroup sleepmgr_group * @{ */ -#if (SAMG) -enum sleepmgr_mode { - //! Active mode. - SLEEPMGR_ACTIVE = 0, - /*! Wait mode. - * Potential Wake Up sources: fast startup events */ - SLEEPMGR_WAIT, - SLEEPMGR_NR_OF_MODES, -}; - -#else enum sleepmgr_mode { //! Active mode. SLEEPMGR_ACTIVE = 0, /*! WFE sleep mode. * Potential Wake Up sources: @@ -78,23 +67,18 @@ * interrupt, and events. */ SLEEPMGR_SLEEP_WFE, /*! WFI sleep mode. * Potential Wake Up sources: fast startup events and interrupt. */ SLEEPMGR_SLEEP_WFI, - /*! Wait mode, wakeup fast (in 3ms). - * XTAL is not disabled when sleep. - * Potential Wake Up sources: fast startup events */ - SLEEPMGR_WAIT_FAST, /*! Wait mode. * Potential Wake Up sources: fast startup events */ SLEEPMGR_WAIT, //! Backup mode. Potential Wake Up sources: WKUPs, SM, RTT, RTC. SLEEPMGR_BACKUP, SLEEPMGR_NR_OF_MODES, }; -#endif /** * \internal * \name Internal arrays * @{ Index: at91lib/peripherals/sleepmgr/sleepmgr.h ================================================================== --- at91lib/peripherals/sleepmgr/sleepmgr.h +++ at91lib/peripherals/sleepmgr/sleepmgr.h @@ -1,11 +1,11 @@ /** * \file * * \brief Sleep manager * - * Copyright (c) 2010 - 2014 Atmel Corporation. All rights reserved. + * Copyright (c) 2010 - 2013 Atmel Corporation. All rights reserved. * * \asf_license_start * * \page License * @@ -44,30 +44,22 @@ #define SLEEPMGR_H #include #include -#if (SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP) +#if (SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S || SAM4E || SAM4N) # include "sam/sleepmgr.h" #elif XMEGA # include "xmega/sleepmgr.h" #elif UC3 # include "uc3/sleepmgr.h" #elif SAM4L # include "sam4l/sleepmgr.h" -#elif MEGA -# include "mega/sleepmgr.h" -#elif (SAMD20 || SAMD21) -# include "samd/sleepmgr.h" #else # error Unsupported device. #endif -#ifdef __cplusplus -extern "C" { -#endif - /** * \defgroup sleepmgr_group Sleep manager * * The sleep manager is a service for ensuring that the device is not put to * sleep in deeper sleep modes than the system (e.g., peripheral drivers, @@ -247,10 +239,6 @@ } //! @} -#ifdef __cplusplus -} -#endif - #endif /* SLEEPMGR_H */ DELETED at91lib/peripherals/uotghs/uotghs_device.c Index: at91lib/peripherals/uotghs/uotghs_device.c ================================================================== --- at91lib/peripherals/uotghs/uotghs_device.c +++ at91lib/peripherals/uotghs/uotghs_device.c @@ -1,2064 +0,0 @@ -/** - * \file - * - * \brief USB Device Driver for UOTGHS. Compliant with common UDD driver. - * - * Copyright (c) 2012 - 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "conf_usb.h" -#include "sysclk.h" -#include "usb/udc/udd.h" -#include "uotghs_otg.h" -#include "uotghs_device.h" -#include - -#ifndef UDD_NO_SLEEP_MGR -# include "pmc/sleep.h" -# include "sleepmgr/sleepmgr.h" -#endif - -#if !(SAM3XA) -# error The current UOTGHS Device Driver supports only SAM3X and SAM3A. -#endif -#ifndef UDD_USB_INT_FUN -# define UDD_USB_INT_FUN UOTGHS_Handler -#endif - -#ifndef UDD_USB_INT_LEVEL -# define UDD_USB_INT_LEVEL 5 // By default USB interrupt have low priority -#endif - -#define UDD_EP_USED(ep) (USB_DEVICE_MAX_EP >= ep) - -#if ( (UDD_EP_USED( 1) && Is_udd_endpoint_dma_supported( 1)) \ - ||(UDD_EP_USED( 2) && Is_udd_endpoint_dma_supported( 2)) \ - ||(UDD_EP_USED( 3) && Is_udd_endpoint_dma_supported( 3)) \ - ||(UDD_EP_USED( 4) && Is_udd_endpoint_dma_supported( 4)) \ - ||(UDD_EP_USED( 5) && Is_udd_endpoint_dma_supported( 5)) \ - ||(UDD_EP_USED( 6) && Is_udd_endpoint_dma_supported( 6)) \ - ||(UDD_EP_USED( 7) && Is_udd_endpoint_dma_supported( 7)) \ - ||(UDD_EP_USED( 8) && Is_udd_endpoint_dma_supported( 8)) \ - ||(UDD_EP_USED( 9) && Is_udd_endpoint_dma_supported( 9)) \ - ||(UDD_EP_USED(10) && Is_udd_endpoint_dma_supported(10)) \ - ||(UDD_EP_USED(11) && Is_udd_endpoint_dma_supported(11)) \ - ||(UDD_EP_USED(12) && Is_udd_endpoint_dma_supported(12)) \ - ||(UDD_EP_USED(13) && Is_udd_endpoint_dma_supported(13)) \ - ||(UDD_EP_USED(14) && Is_udd_endpoint_dma_supported(14)) \ - ||(UDD_EP_USED(15) && Is_udd_endpoint_dma_supported(15)) \ - ) -# define UDD_EP_DMA_SUPPORTED -#endif - -#if ( (UDD_EP_USED( 1) && !Is_udd_endpoint_dma_supported( 1)) \ - ||(UDD_EP_USED( 2) && !Is_udd_endpoint_dma_supported( 2)) \ - ||(UDD_EP_USED( 3) && !Is_udd_endpoint_dma_supported( 3)) \ - ||(UDD_EP_USED( 4) && !Is_udd_endpoint_dma_supported( 4)) \ - ||(UDD_EP_USED( 5) && !Is_udd_endpoint_dma_supported( 5)) \ - ||(UDD_EP_USED( 6) && !Is_udd_endpoint_dma_supported( 6)) \ - ||(UDD_EP_USED( 7) && !Is_udd_endpoint_dma_supported( 7)) \ - ||(UDD_EP_USED( 8) && !Is_udd_endpoint_dma_supported( 8)) \ - ||(UDD_EP_USED( 9) && !Is_udd_endpoint_dma_supported( 9)) \ - ||(UDD_EP_USED(10) && !Is_udd_endpoint_dma_supported(10)) \ - ||(UDD_EP_USED(11) && !Is_udd_endpoint_dma_supported(11)) \ - ||(UDD_EP_USED(12) && !Is_udd_endpoint_dma_supported(12)) \ - ||(UDD_EP_USED(13) && !Is_udd_endpoint_dma_supported(13)) \ - ||(UDD_EP_USED(14) && !Is_udd_endpoint_dma_supported(14)) \ - ||(UDD_EP_USED(15) && !Is_udd_endpoint_dma_supported(15)) \ - ) -# define UDD_EP_FIFO_SUPPORTED -#endif - -// for debug text -//#define dbg_print printf -#define dbg_print(...) - -/** - * \ingroup udd_group - * \defgroup udd_udphs_group USB On-The-Go High-Speed Port for device mode (UOTGHS) - * - * \section UOTGHS_CONF UOTGHS Custom configuration - * The following UOTGHS driver configuration must be included in the conf_usb.h - * file of the application. - * - * UDD_USB_INT_LEVEL
- * Option to change the interrupt priority (0 to 15) by default 5 (recommended). - * - * UDD_USB_INT_FUN
- * Option to fit interrupt function to what defined in exception table. - * - * UDD_ISOCHRONOUS_NB_BANK(ep)
- * Feature to reduce or increase isochronous endpoints buffering (1 to 3). - * Default value 2. - * - * UDD_BULK_NB_BANK(ep)
- * Feature to reduce or increase bulk endpoints buffering (1 to 2). - * Default value 2. - * - * UDD_INTERRUPT_NB_BANK(ep)
- * Feature to reduce or increase interrupt endpoints buffering (1 to 2). - * Default value 1. - * - * \section Callbacks management - * The USB driver is fully managed by interrupt and does not request periodique - * task. Thereby, the USB events use callbacks to transfer the information. - * The callbacks are declared in static during compilation or in variable during - * code execution. - * - * Static declarations defined in conf_usb.h: - * - UDC_VBUS_EVENT(bool b_present)
- * To signal Vbus level change - * - UDC_SUSPEND_EVENT()
- * Called when USB bus enter in suspend mode - * - UDC_RESUME_EVENT()
- * Called when USB bus is wakeup - * - UDC_SOF_EVENT()
- * Called for each received SOF, Note: Each 1ms in HS/FS mode only. - * - * Dynamic callbacks, called "endpoint job" , are registered - * in udd_ep_job_t structure via the following functions: - * - udd_ep_run()
- * To call it when a transfer is finish - * - udd_ep_wait_stall_clear()
- * To call it when a endpoint halt is disabled - * - * \section Power mode management - * The Sleep modes authorized : - * - in USB IDLE state, the UOTGHS needs of USB clock and authorizes up to sleep mode WFI. - * - in USB SUSPEND state, the UOTGHS no needs USB clock and authorizes up to sleep mode WAIT. - * @{ - */ - -// Check USB Device configuration -#ifndef USB_DEVICE_EP_CTRL_SIZE -# error USB_DEVICE_EP_CTRL_SIZE not defined -#endif -#ifndef USB_DEVICE_MAX_EP -# error USB_DEVICE_MAX_EP not defined -#endif - -// Note: USB_DEVICE_MAX_EP does not include control endpoint -#if USB_DEVICE_MAX_EP > (UDD_MAX_PEP_NB-1) -# error USB_DEVICE_MAX_EP is too high and not supported by this part -#endif - -#define UDD_EP_ISO_NBANK_ERROR(ep) \ - ( (UDD_ISOCHRONOUS_NB_BANK(ep) < 1) \ - || (UDD_ISOCHRONOUS_NB_BANK(ep) > 3) ) -#define UDD_EP_BULK_NBANK_ERROR(ep) \ - ( (UDD_BULK_NB_BANK(ep) < 1) || (UDD_BULK_NB_BANK(ep) > 2) ) -#define UDD_EP_INT_NBANK_ERROR(ep) \ - ( (UDD_INTERRUPT_NB_BANK(ep) < 1) || (UDD_INTERRUPT_NB_BANK(ep) > 2) ) - -#define UDD_EP_ISO_NB_BANK_ERROR(ep) \ - (UDD_EP_USED(ep) && UDD_EP_ISO_NBANK_ERROR(ep)) -#define UDD_EP_BULK_NB_BANK_ERROR(ep) \ - (UDD_EP_USED(ep) && UDD_EP_ISO_NBANK_ERROR(ep)) -#define UDD_EP_INT_NB_BANK_ERROR(ep) \ - (UDD_EP_USED(ep) && UDD_EP_ISO_NBANK_ERROR(ep)) - -#define UDD_EP_NB_BANK_ERROR(ep, type) \ - (ATPASTE3(UDD_EP_, type, _NB_BANK_ERROR(ep))) - -#define UDD_ISO_NB_BANK_ERROR \ - ( UDD_EP_NB_BANK_ERROR( 1, ISO) \ - || UDD_EP_NB_BANK_ERROR( 2, ISO) \ - || UDD_EP_NB_BANK_ERROR( 3, ISO) \ - || UDD_EP_NB_BANK_ERROR( 4, ISO) \ - || UDD_EP_NB_BANK_ERROR( 5, ISO) \ - || UDD_EP_NB_BANK_ERROR( 6, ISO) \ - || UDD_EP_NB_BANK_ERROR( 7, ISO) \ - || UDD_EP_NB_BANK_ERROR( 8, ISO) \ - || UDD_EP_NB_BANK_ERROR( 9, ISO) \ - || UDD_EP_NB_BANK_ERROR(10, ISO) \ - || UDD_EP_NB_BANK_ERROR(11, ISO) \ - || UDD_EP_NB_BANK_ERROR(12, ISO) \ - || UDD_EP_NB_BANK_ERROR(13, ISO) \ - || UDD_EP_NB_BANK_ERROR(14, ISO) \ - || UDD_EP_NB_BANK_ERROR(15, ISO) ) -#define UDD_BULK_NB_BANK_ERROR \ - ( UDD_EP_NB_BANK_ERROR( 1, BULK) \ - || UDD_EP_NB_BANK_ERROR( 2, BULK) \ - || UDD_EP_NB_BANK_ERROR( 3, BULK) \ - || UDD_EP_NB_BANK_ERROR( 4, BULK) \ - || UDD_EP_NB_BANK_ERROR( 5, BULK) \ - || UDD_EP_NB_BANK_ERROR( 6, BULK) \ - || UDD_EP_NB_BANK_ERROR( 7, BULK) \ - || UDD_EP_NB_BANK_ERROR( 8, BULK) \ - || UDD_EP_NB_BANK_ERROR( 9, BULK) \ - || UDD_EP_NB_BANK_ERROR(10, BULK) \ - || UDD_EP_NB_BANK_ERROR(11, BULK) \ - || UDD_EP_NB_BANK_ERROR(12, BULK) \ - || UDD_EP_NB_BANK_ERROR(13, BULK) \ - || UDD_EP_NB_BANK_ERROR(14, BULK) \ - || UDD_EP_NB_BANK_ERROR(15, BULK) ) -#define UDD_INTERRUPT_NB_BANK_ERROR \ - ( UDD_EP_NB_BANK_ERROR( 1, INT) \ - || UDD_EP_NB_BANK_ERROR( 2, INT) \ - || UDD_EP_NB_BANK_ERROR( 3, INT) \ - || UDD_EP_NB_BANK_ERROR( 4, INT) \ - || UDD_EP_NB_BANK_ERROR( 5, INT) \ - || UDD_EP_NB_BANK_ERROR( 6, INT) \ - || UDD_EP_NB_BANK_ERROR( 7, INT) \ - || UDD_EP_NB_BANK_ERROR( 8, INT) \ - || UDD_EP_NB_BANK_ERROR( 9, INT) \ - || UDD_EP_NB_BANK_ERROR(10, INT) \ - || UDD_EP_NB_BANK_ERROR(11, INT) \ - || UDD_EP_NB_BANK_ERROR(12, INT) \ - || UDD_EP_NB_BANK_ERROR(13, INT) \ - || UDD_EP_NB_BANK_ERROR(14, INT) \ - || UDD_EP_NB_BANK_ERROR(15, INT) ) - -#ifndef UDD_ISOCHRONOUS_NB_BANK -# define UDD_ISOCHRONOUS_NB_BANK(ep) 2 -#else -# if UDD_ISO_NB_BANK_ERROR -# error UDD_ISOCHRONOUS_NB_BANK(ep) must be define within 1 to 3. -# endif -#endif - -#ifndef UDD_BULK_NB_BANK -# define UDD_BULK_NB_BANK(ep) 2 -#else -# if UDD_BULK_NB_BANK_ERROR -# error UDD_BULK_NB_BANK must be define with 1 or 2. -# endif -#endif - -#ifndef UDD_INTERRUPT_NB_BANK -# define UDD_INTERRUPT_NB_BANK(ep) 1 -#else -# if UDD_INTERRUPT_NB_BANK_ERROR -# error UDD_INTERRUPT_NB_BANK must be define with 1 or 2. -# endif -#endif - - -/** - * \name Power management routine. - */ -//@{ - -#ifndef UDD_NO_SLEEP_MGR - -//! Definition of sleep levels -#define UOTGHS_SLEEP_MODE_USB_SUSPEND SLEEPMGR_WAIT_FAST -#define UOTGHS_SLEEP_MODE_USB_IDLE SLEEPMGR_SLEEP_WFI - -//! State of USB line -static bool udd_b_idle; -//! State of sleep manager -static bool udd_b_sleep_initialized = false; - - -/*! \brief Authorize or not the CPU powerdown mode - * - * \param b_enable true to authorize idle mode - */ -static void udd_sleep_mode(bool b_idle) -{ - if (!b_idle && udd_b_idle) { - dbg_print("_S "); - sleepmgr_unlock_mode(UOTGHS_SLEEP_MODE_USB_IDLE); - } - if (b_idle && !udd_b_idle) { - dbg_print("_W "); - sleepmgr_lock_mode(UOTGHS_SLEEP_MODE_USB_IDLE); - } - udd_b_idle = b_idle; -} -#else - -static void udd_sleep_mode(bool b_idle) -{ - b_idle = b_idle; -} - -#endif // UDD_NO_SLEEP_MGR - -//@} - - -/** - * \name Control endpoint low level management routine. - * - * This function performs control endpoint mangement. - * It handle the SETUP/DATA/HANDSHAKE phases of a control transaction. - */ -//@{ - -//! Global variable to give and record information about setup request management -COMPILER_WORD_ALIGNED udd_ctrl_request_t udd_g_ctrlreq; - -//! Bit definitions about endpoint control state machine for udd_ep_control_state -typedef enum { - UDD_EPCTRL_SETUP = 0, //!< Wait a SETUP packet - UDD_EPCTRL_DATA_OUT = 1, //!< Wait a OUT data packet - UDD_EPCTRL_DATA_IN = 2, //!< Wait a IN data packet - UDD_EPCTRL_HANDSHAKE_WAIT_IN_ZLP = 3, //!< Wait a IN ZLP packet - UDD_EPCTRL_HANDSHAKE_WAIT_OUT_ZLP = 4, //!< Wait a OUT ZLP packet - UDD_EPCTRL_STALL_REQ = 5, //!< STALL enabled on IN & OUT packet -} udd_ctrl_ep_state_t; - -//! State of the endpoint control management -static udd_ctrl_ep_state_t udd_ep_control_state; - -//! Total number of data received/sent during data packet phase with previous payload buffers -static uint16_t udd_ctrl_prev_payload_buf_cnt; - -//! Number of data received/sent to/from udd_g_ctrlreq.payload buffer -static uint16_t udd_ctrl_payload_buf_cnt; - -/** - * \brief Reset control endpoint - * - * Called after a USB line reset or when UDD is enabled - */ -static void udd_reset_ep_ctrl(void); - -/** - * \brief Reset control endpoint management - * - * Called after a USB line reset or at the end of SETUP request (after ZLP) - */ -static void udd_ctrl_init(void); - -//! \brief Managed reception of SETUP packet on control endpoint -static void udd_ctrl_setup_received(void); - -//! \brief Managed reception of IN packet on control endpoint -static void udd_ctrl_in_sent(void); - -//! \brief Managed reception of OUT packet on control endpoint -static void udd_ctrl_out_received(void); - -//! \brief Managed underflow event of IN packet on control endpoint -static void udd_ctrl_underflow(void); - -//! \brief Managed overflow event of OUT packet on control endpoint -static void udd_ctrl_overflow(void); - -//! \brief Managed stall event of IN/OUT packet on control endpoint -static void udd_ctrl_stall_data(void); - -//! \brief Send a ZLP IN on control endpoint -static void udd_ctrl_send_zlp_in(void); - -//! \brief Send a ZLP OUT on control endpoint -static void udd_ctrl_send_zlp_out(void); - -//! \brief Call callback associated to setup request -static void udd_ctrl_endofrequest(void); - - -/** - * \brief Main interrupt routine for control endpoint - * - * This switchs control endpoint events to correct sub function. - * - * \return \c 1 if an event about control endpoint is occured, otherwise \c 0. - */ -static bool udd_ctrl_interrupt(void); - -//@} - - -/** - * \name Management of bulk/interrupt/isochronous endpoints - * - * The UDD manages the data transfer on endpoints: - * - Start data tranfer on endpoint with USB Device DMA - * - Send a ZLP packet if requested - * - Call callback registered to signal end of transfer - * The transfer abort and stall feature are supported. - */ -//@{ -#if (0!=USB_DEVICE_MAX_EP) - -//! Structure definition about job registered on an endpoint -typedef struct { - union { - //! Callback to call at the end of transfer - udd_callback_trans_t call_trans; - - //! Callback to call when the endpoint halt is cleared - udd_callback_halt_cleared_t call_nohalt; - }; - //! Buffer located in internal RAM to send or fill during job - uint8_t *buf; - //! Size of buffer to send or fill - iram_size_t buf_size; - //!< Size of data transfered - iram_size_t buf_cnt; - //!< Size of data loaded (or prepared for DMA) last time - iram_size_t buf_load; - //! A job is registered on this endpoint - uint8_t busy:1; - //! A short packet is requested for this job on endpoint IN - uint8_t b_shortpacket:1; - //! A stall has been requested but not executed - uint8_t stall_requested:1; -} udd_ep_job_t; - - -//! Array to register a job on bulk/interrupt/isochronous endpoint -static udd_ep_job_t udd_ep_job[USB_DEVICE_MAX_EP]; - -//! \brief Reset all job table -static void udd_ep_job_table_reset(void); - -//! \brief Abort all endpoint jobs on going -static void udd_ep_job_table_kill(void); - -#ifdef UDD_EP_FIFO_SUPPORTED - /** - * \brief Fill banks and send them - * - * \param ep endpoint number of job to abort - */ - static void udd_ep_in_sent(udd_ep_id_t ep); - - /** - * \brief Store received banks - * - * \param ep endpoint number of job to abort - */ - static void udd_ep_out_received(udd_ep_id_t ep); -#endif - -/** - * \brief Abort endpoint job on going - * - * \param ep endpoint number of job to abort - */ -static void udd_ep_abort_job(udd_ep_id_t ep); - -/** - * \brief Call the callback associated to the job which is finished - * - * \param ptr_job job to complete - * \param b_abort if true then the job has been aborted - */ -static void udd_ep_finish_job(udd_ep_job_t * ptr_job, bool b_abort, uint8_t ep_num); - -#ifdef UDD_EP_DMA_SUPPORTED - /** - * \brief Start the next transfer if necessary or complet the job associated. - * - * \param ep endpoint number without direction flag - */ - static void udd_ep_trans_done(udd_ep_id_t ep); -#endif - -/** - * \brief Main interrupt routine for bulk/interrupt/isochronous endpoints - * - * This switchs endpoint events to correct sub function. - * - * \return \c 1 if an event about bulk/interrupt/isochronous endpoints has occured, otherwise \c 0. - */ -static bool udd_ep_interrupt(void); - -#endif // (0!=USB_DEVICE_MAX_EP) -//@} - - -//-------------------------------------------------------- -//--- INTERNAL ROUTINES TO MANAGED GLOBAL EVENTS - -/** - * \internal - * \brief Function called by UOTGHS interrupt to manage USB Device interrupts - * - * USB Device interrupt events are splited in three parts: - * - USB line events (SOF, reset, suspend, resume, wakeup) - * - control endpoint events (setup reception, end of data transfer, underflow, overflow, stall) - * - bulk/interrupt/isochronous endpoints events (end of data transfer) - * - * Note: - * Here, the global interrupt mask is not clear when an USB interrupt is enabled - * because this one can not be occured during the USB ISR (=during INTX is masked). - * See Technical reference $3.8.3 Masking interrupt requests in peripheral modules. - */ -#ifdef UHD_ENABLE -void udd_interrupt(void); -void udd_interrupt(void) -#else -ISR(UDD_USB_INT_FUN) -#endif -{ - /* For fast wakeup clocks restore - * In WAIT mode, clocks are switched to FASTRC. - * After wakeup clocks should be restored, before that ISR should not - * be served. - */ - if (!pmc_is_wakeup_clocks_restored() && !Is_udd_suspend()) { - cpu_irq_disable(); - return; - } - - if (Is_udd_sof()) { - udd_ack_sof(); - if (Is_udd_full_speed_mode()) { - udc_sof_notify(); - } -#ifdef UDC_SOF_EVENT - UDC_SOF_EVENT(); -#endif - goto udd_interrupt_sof_end; - } - - if (Is_udd_msof()) { - udd_ack_msof(); - udc_sof_notify(); - goto udd_interrupt_sof_end; - } - - dbg_print("%c ", udd_is_high_speed() ? 'H' : 'F'); - - if (udd_ctrl_interrupt()) { - goto udd_interrupt_end; // Interrupt acked by control endpoint managed - } - -#if (0 != USB_DEVICE_MAX_EP) - if (udd_ep_interrupt()) { - goto udd_interrupt_end; // Interrupt acked by bulk/interrupt/isochronous endpoint managed - } -#endif - - // USB bus reset detection - if (Is_udd_reset()) { - udd_ack_reset(); - dbg_print("RST "); - // Abort all jobs on-going -#if (USB_DEVICE_MAX_EP != 0) - udd_ep_job_table_kill(); -#endif - // Reset USB Device Stack Core - udc_reset(); - // Reset endpoint control - udd_reset_ep_ctrl(); - // Reset endpoint control management - udd_ctrl_init(); - goto udd_interrupt_end; - } - - if (Is_udd_suspend_interrupt_enabled() && Is_udd_suspend()) { - otg_unfreeze_clock(); - // The suspend interrupt is automatic acked when a wakeup occur - udd_disable_suspend_interrupt(); - udd_enable_wake_up_interrupt(); - otg_freeze_clock(); // Mandatory to exit of sleep mode after a wakeup event - udd_sleep_mode(false); // Enter in SUSPEND mode -#ifdef UDC_SUSPEND_EVENT - UDC_SUSPEND_EVENT(); -#endif - goto udd_interrupt_end; - } - - if (Is_udd_wake_up_interrupt_enabled() && Is_udd_wake_up()) { - // Ack wakeup interrupt and enable suspend interrupt - otg_unfreeze_clock(); - // Check USB clock ready after suspend and eventually sleep USB clock - while (!Is_otg_clock_usable()) { - if (Is_udd_suspend()) { - break; // In case of USB state change in HS - } - }; - // The wakeup interrupt is automatic acked when a suspend occur - udd_disable_wake_up_interrupt(); - udd_enable_suspend_interrupt(); - udd_sleep_mode(true); // Enter in IDLE mode -#ifdef UDC_RESUME_EVENT - UDC_RESUME_EVENT(); -#endif - goto udd_interrupt_end; - } - - if (Is_otg_vbus_transition()) { - dbg_print("VBus "); - // Ack Vbus transition and send status to high level - otg_unfreeze_clock(); - otg_ack_vbus_transition(); - otg_freeze_clock(); -#ifndef USB_DEVICE_ATTACH_AUTO_DISABLE - if (Is_otg_vbus_high()) { - udd_attach(); - } else { - udd_detach(); - } -#endif -#ifdef UDC_VBUS_EVENT - UDC_VBUS_EVENT(Is_otg_vbus_high()); -#endif - goto udd_interrupt_end; - } -udd_interrupt_end: - dbg_print("\n\r"); -udd_interrupt_sof_end: - return; -} - - -bool udd_include_vbus_monitoring(void) -{ - return true; -} - - -void udd_enable(void) -{ - irqflags_t flags; - - flags = cpu_irq_save(); - -#ifdef UHD_ENABLE - // DUAL ROLE INITIALIZATION - if (otg_dual_enable()) { - // The current mode has been started by otg_dual_enable() - cpu_irq_restore(flags); - return; - } -#else - // SINGLE DEVICE MODE INITIALIZATION - pmc_enable_periph_clk(ID_UOTGHS); - sysclk_enable_usb(); - - // Here, only the device mode is possible, then link UOTGHS interrupt to UDD interrupt - NVIC_SetPriority((IRQn_Type) ID_UOTGHS, UDD_USB_INT_LEVEL); - NVIC_EnableIRQ((IRQn_Type) ID_UOTGHS); - - // Always authorize asynchrone USB interrupts to exit of sleep mode - // For SAM USB wake up device except BACKUP mode - pmc_set_fast_startup_input(PMC_FSMR_USBAL); -#endif - -#if (defined USB_ID_GPIO) && (defined UHD_ENABLE) - // Check that the device mode is selected by ID pin - if (!Is_otg_id_device()) { - cpu_irq_restore(flags); - return; // Device is not the current mode - } -#else - // ID pin not used then force device mode - otg_disable_id_pin(); - otg_force_device_mode(); -#endif - // Enable USB hardware - otg_enable_pad(); - otg_enable(); - - // Set the USB speed requested by configuration file -#ifdef USB_DEVICE_LOW_SPEED - udd_low_speed_enable(); -#else - udd_low_speed_disable(); -# ifdef USB_DEVICE_HS_SUPPORT - udd_high_speed_enable(); -# else - udd_high_speed_disable(); -# endif -#endif // USB_DEVICE_LOW_SPEED - - // Check USB clock - otg_unfreeze_clock(); - while (!Is_otg_clock_usable()); - - // Reset internal variables -#if (0!=USB_DEVICE_MAX_EP) - udd_ep_job_table_reset(); -#endif - - otg_ack_vbus_transition(); - // Force Vbus interrupt in case of Vbus always with a high level - // This is possible with a short timing between a Host mode stop/start. - if (Is_otg_vbus_high()) { - otg_raise_vbus_transition(); - } - otg_enable_vbus_interrupt(); - otg_freeze_clock(); - -#ifndef UDD_NO_SLEEP_MGR - if (!udd_b_sleep_initialized) { - udd_b_sleep_initialized = true; - // Initialize the sleep mode authorized for the USB suspend mode - udd_b_idle = false; - sleepmgr_lock_mode(UOTGHS_SLEEP_MODE_USB_SUSPEND); - } else { - udd_sleep_mode(false); // Enter idle mode - } -#endif - - cpu_irq_restore(flags); -} - - -void udd_disable(void) -{ - irqflags_t flags; - -#ifdef UHD_ENABLE -# ifdef USB_ID_GPIO - if (Is_otg_id_host()) { - // Freeze clock to switch mode - otg_freeze_clock(); - udd_detach(); - otg_disable(); - return; // Host mode running, ignore UDD disable - } -# else - if (Is_otg_host_mode_forced()) { - return; // Host mode running, ignore UDD disable - } -# endif -#endif - - flags = cpu_irq_save(); - otg_unfreeze_clock(); - udd_detach(); -#ifndef UDD_NO_SLEEP_MGR - if (udd_b_sleep_initialized) { - udd_b_sleep_initialized = false; - sleepmgr_unlock_mode(UOTGHS_SLEEP_MODE_USB_SUSPEND); - } -#endif - -#ifndef UHD_ENABLE - otg_disable(); - otg_disable_pad(); - sysclk_disable_usb(); - pmc_disable_periph_clk(ID_UOTGHS); - // Else the USB clock disable is done by UHC which manage USB dual role -#endif - cpu_irq_restore(flags); -} - - -void udd_attach(void) -{ - irqflags_t flags; - flags = cpu_irq_save(); - - // At startup the USB bus state is unknown, - // therefore the state is considered IDLE to not miss any USB event - udd_sleep_mode(true); - otg_unfreeze_clock(); - - // This section of clock check can be improved with a chek of - // USB clock source via sysclk() - // Check USB clock because the source can be a PLL - while (!Is_otg_clock_usable()); - - // Authorize attach if Vbus is present - udd_attach_device(); - - // Enable USB line events - udd_enable_reset_interrupt(); - udd_enable_suspend_interrupt(); - udd_enable_wake_up_interrupt(); - udd_enable_sof_interrupt(); -#ifdef USB_DEVICE_HS_SUPPORT - udd_enable_msof_interrupt(); -#endif - // Reset following interupts flag - udd_ack_reset(); - udd_ack_sof(); - udd_ack_msof(); - - // The first suspend interrupt must be forced - // The first suspend interrupt is not detected else raise it - udd_raise_suspend(); - - udd_ack_wake_up(); - otg_freeze_clock(); - cpu_irq_restore(flags); -} - - -void udd_detach(void) -{ - otg_unfreeze_clock(); - - // Detach device from the bus - udd_detach_device(); - otg_freeze_clock(); - udd_sleep_mode(false); -} - - -bool udd_is_high_speed(void) -{ -#ifdef USB_DEVICE_HS_SUPPORT - return !Is_udd_full_speed_mode(); -#else - return false; -#endif -} - - -void udd_set_address(uint8_t address) -{ - udd_disable_address(); - udd_configure_address(address); - udd_enable_address(); -} - - -uint8_t udd_getaddress(void) -{ - return udd_get_configured_address(); -} - - -uint16_t udd_get_frame_number(void) -{ - return udd_frame_number(); -} - -uint16_t udd_get_micro_frame_number(void) -{ - return udd_micro_frame_number(); -} - -void udd_send_remotewakeup(void) -{ -#ifndef UDD_NO_SLEEP_MGR - if (!udd_b_idle) -#endif - { - udd_sleep_mode(true); // Enter in IDLE mode - otg_unfreeze_clock(); - udd_initiate_remote_wake_up(); - } -} - - -void udd_set_setup_payload(uint8_t *payload, uint16_t payload_size) -{ - udd_g_ctrlreq.payload = payload; - udd_g_ctrlreq.payload_size = payload_size; -} - - -#if (0 != USB_DEVICE_MAX_EP) -bool udd_ep_alloc(udd_ep_id_t ep, uint8_t bmAttributes, - uint16_t MaxEndpointSize) -{ - bool b_dir_in; - uint16_t ep_allocated; - uint8_t nb_bank, bank, i; - - b_dir_in = ep & USB_EP_DIR_IN; - ep = ep & USB_EP_ADDR_MASK; - - if (ep > USB_DEVICE_MAX_EP) { - return false; - } - if (Is_udd_endpoint_enabled(ep)) { - return false; - } - dbg_print("alloc(%x, %d) ", ep, MaxEndpointSize); - - // Bank choise - switch (bmAttributes & USB_EP_TYPE_MASK) { - case USB_EP_TYPE_ISOCHRONOUS: - nb_bank = UDD_ISOCHRONOUS_NB_BANK(ep); - break; - case USB_EP_TYPE_INTERRUPT: - nb_bank = UDD_INTERRUPT_NB_BANK(ep); - break; - case USB_EP_TYPE_BULK: - nb_bank = UDD_BULK_NB_BANK(ep); - break; - default: - Assert(false); - return false; - } - switch (nb_bank) { - case 1: - bank = UOTGHS_DEVEPTCFG_EPBK_1_BANK >> - UOTGHS_DEVEPTCFG_EPBK_Pos; - break; - case 2: - bank = UOTGHS_DEVEPTCFG_EPBK_2_BANK >> - UOTGHS_DEVEPTCFG_EPBK_Pos; - break; - case 3: - bank = UOTGHS_DEVEPTCFG_EPBK_3_BANK >> - UOTGHS_DEVEPTCFG_EPBK_Pos; - break; - default: - Assert(false); - return false; - } - - // Check if endpoint size is 8,16,32,64,128,256,512 or 1023 - Assert(MaxEndpointSize < 1024); - Assert((MaxEndpointSize == 1023) - || !(MaxEndpointSize & (MaxEndpointSize - 1))); - Assert(MaxEndpointSize >= 8); - - // Set configuration of new endpoint - udd_configure_endpoint(ep, bmAttributes, (b_dir_in ? 1 : 0), - MaxEndpointSize, bank); - ep_allocated = 1 << ep; - - // Unalloc endpoints superior - for (i = USB_DEVICE_MAX_EP; i > ep; i--) { - if (Is_udd_endpoint_enabled(i)) { - ep_allocated |= 1 << i; - udd_disable_endpoint(i); - udd_unallocate_memory(i); - } - } - - // Realloc/Enable endpoints - for (i = ep; i <= USB_DEVICE_MAX_EP; i++) { - if (ep_allocated & (1 << i)) { - udd_ep_job_t *ptr_job = &udd_ep_job[i - 1]; - bool b_restart = ptr_job->busy; - // Restart running job because - // memory window slides up and its data is lost - ptr_job->busy = false; - // Re-allocate memory - udd_allocate_memory(i); - udd_enable_endpoint(i); - if (!Is_udd_endpoint_configured(i)) { - dbg_print("ErrRealloc%d ", i); - if (NULL == ptr_job->call_trans) { - return false; - } - if (Is_udd_endpoint_in(i)) { - i |= USB_EP_DIR_IN; - } - ptr_job->call_trans(UDD_EP_TRANSFER_ABORT, - ptr_job->buf_cnt, i); - return false; - } - udd_enable_endpoint_bank_autoswitch(i); - if (b_restart) { - // Re-run the job remaining part -# ifdef UDD_EP_FIFO_SUPPORTED - if (!Is_udd_endpoint_dma_supported(i) - && !Is_udd_endpoint_in(i)) { - ptr_job->buf_cnt -= ptr_job->buf_load; - } -# else - ptr_job->buf_cnt -= ptr_job->buf_load; -# endif - b_restart = udd_ep_run(Is_udd_endpoint_in(i) ? - (i | USB_EP_DIR_IN) : i, - ptr_job->b_shortpacket, - &ptr_job->buf[ptr_job->buf_cnt], - ptr_job->buf_size - - ptr_job->buf_cnt, - ptr_job->call_trans); - if (!b_restart) { - dbg_print("ErrReRun%d ", i); - return false; - } - } - } - } - return true; -} - - -void udd_ep_free(udd_ep_id_t ep) -{ - uint8_t ep_index = ep & USB_EP_ADDR_MASK; - if (USB_DEVICE_MAX_EP < ep_index) { - return; - } - udd_disable_endpoint(ep_index); - udd_unallocate_memory(ep_index); - udd_ep_abort_job(ep); - udd_ep_job[ep_index - 1].stall_requested = false; -} - - -bool udd_ep_is_halted(udd_ep_id_t ep) -{ - uint8_t ep_index = ep & USB_EP_ADDR_MASK; - return Is_udd_endpoint_stall_requested(ep_index); -} - - -bool udd_ep_set_halt(udd_ep_id_t ep) -{ - uint8_t ep_index = ep & USB_EP_ADDR_MASK; - udd_ep_job_t *ptr_job = &udd_ep_job[ep_index - 1]; - irqflags_t flags; - - if (USB_DEVICE_MAX_EP < ep_index) { - return false; - } - - if (Is_udd_endpoint_stall_requested(ep_index) // Endpoint stalled - || ptr_job->stall_requested) { // Endpoint stall is requested - return true; // Already STALL - } - - if (ptr_job->busy == true) { - return false; // Job on going, stall impossible - } - - flags = cpu_irq_save(); - if ((ep & USB_EP_DIR_IN) && (0 != udd_nb_busy_bank(ep_index))) { - // Delay the stall after the end of IN transfer on USB line - ptr_job->stall_requested = true; -#ifdef UDD_EP_FIFO_SUPPORTED - udd_disable_in_send_interrupt(ep_index); - udd_enable_endpoint_bank_autoswitch(ep_index); -#endif - udd_enable_bank_interrupt(ep_index); - udd_enable_endpoint_interrupt(ep_index); - cpu_irq_restore(flags); - return true; - } - // Stall endpoint immediately - udd_disable_endpoint_bank_autoswitch(ep_index); - udd_ack_stall(ep_index); - udd_enable_stall_handshake(ep_index); - cpu_irq_restore(flags); - return true; -} - - -bool udd_ep_clear_halt(udd_ep_id_t ep) -{ - uint8_t ep_index = ep & USB_EP_ADDR_MASK; - udd_ep_job_t *ptr_job = &udd_ep_job[ep_index - 1]; - bool b_stall_cleared = false; - - if (USB_DEVICE_MAX_EP < ep_index) - return false; - - if (ptr_job->stall_requested) { - // Endpoint stall has been requested but not done - // Remove stall request - ptr_job->stall_requested = false; - udd_disable_bank_interrupt(ep_index); - udd_disable_endpoint_interrupt(ep_index); - b_stall_cleared = true; - } - if (Is_udd_endpoint_stall_requested(ep_index)) { - if (Is_udd_stall(ep_index)) { - udd_ack_stall(ep_index); - // A packet has been stalled - // then reset datatoggle - udd_reset_data_toggle(ep_index); - } - // Disable stall - udd_disable_stall_handshake(ep_index); - udd_enable_endpoint_bank_autoswitch(ep_index); - b_stall_cleared = true; - } - if (b_stall_cleared) { - // If a job is register on clear halt action - // then execute callback - if (ptr_job->busy == true) { - ptr_job->busy = false; - ptr_job->call_nohalt(); - } - } - return true; -} - - -bool udd_ep_run(udd_ep_id_t ep, bool b_shortpacket, - uint8_t * buf, iram_size_t buf_size, - udd_callback_trans_t callback) -{ -#ifdef UDD_EP_FIFO_SUPPORTED - bool b_dir_in = Is_udd_endpoint_in(ep & USB_EP_ADDR_MASK); -#endif - udd_ep_job_t *ptr_job; - irqflags_t flags; - - ep &= USB_EP_ADDR_MASK; - if (USB_DEVICE_MAX_EP < ep) { - return false; - } - - // Get job about endpoint - ptr_job = &udd_ep_job[ep - 1]; - - if ((!Is_udd_endpoint_enabled(ep)) - || Is_udd_endpoint_stall_requested(ep) - || ptr_job->stall_requested) { - return false; // Endpoint is halted - } - - flags = cpu_irq_save(); - if (ptr_job->busy == true) { - cpu_irq_restore(flags); - return false; // Job already on going - } - ptr_job->busy = true; - cpu_irq_restore(flags); - - // No job running. Let's setup a new one. - ptr_job->buf = buf; - ptr_job->buf_size = buf_size; - ptr_job->buf_cnt = 0; - ptr_job->buf_load = 0; - ptr_job->call_trans = callback; - ptr_job->b_shortpacket = b_shortpacket || (buf_size == 0); - -#ifdef UDD_EP_FIFO_SUPPORTED - // No DMA support - if (!Is_udd_endpoint_dma_supported(ep)) { - dbg_print("ex%x.%c%d\n\r", ep, b_dir_in ? 'i':'o', buf_size); - flags = cpu_irq_save(); - udd_enable_endpoint_interrupt(ep); - if (b_dir_in) { - udd_disable_endpoint_bank_autoswitch(ep); - udd_enable_in_send_interrupt(ep); - } else { - udd_disable_endpoint_bank_autoswitch(ep); - udd_enable_out_received_interrupt(ep); - } - cpu_irq_restore(flags); - return true; - } -#endif // UDD_EP_FIFO_SUPPORTED - -#ifdef UDD_EP_DMA_SUPPORTED - // Request first DMA transfer - dbg_print("(exDMA%x) ", ep); - udd_ep_trans_done(ep); - return true; -#endif -} - - -void udd_ep_abort(udd_ep_id_t ep) -{ - uint8_t ep_index = ep & USB_EP_ADDR_MASK; - -#ifdef UDD_EP_FIFO_SUPPORTED - if (!Is_udd_endpoint_dma_supported(ep_index)) { - // Disable interrupts - udd_disable_endpoint_interrupt(ep_index); - udd_disable_out_received_interrupt(ep_index); - udd_disable_in_send_interrupt(ep_index); - } else -#endif - { - // Stop DMA transfer - udd_disable_endpoint_dma_interrupt(ep_index); - udd_endpoint_dma_set_control(ep_index, 0); - } - udd_disable_endpoint_interrupt(ep_index); - // Kill IN banks - if (ep & USB_EP_DIR_IN) { - while(udd_nb_busy_bank(ep_index)) { - udd_kill_last_in_bank(ep_index); - while(Is_udd_kill_last(ep_index)); - } - } - udd_ep_abort_job(ep); -} - - -bool udd_ep_wait_stall_clear(udd_ep_id_t ep, - udd_callback_halt_cleared_t callback) -{ - udd_ep_job_t *ptr_job; - - ep &= USB_EP_ADDR_MASK; - if (USB_DEVICE_MAX_EP < ep) { - return false; - } - - ptr_job = &udd_ep_job[ep - 1]; - - if (!Is_udd_endpoint_enabled(ep)) { - return false; // Endpoint not enabled - } - - // Wait clear halt endpoint - if (ptr_job->busy == true) { - return false; // Job already on going - } - - if (Is_udd_endpoint_stall_requested(ep) - || ptr_job->stall_requested) { - // Endpoint halted then registes the callback - ptr_job->busy = true; - ptr_job->call_nohalt = callback; - } else { - // endpoint not halted then call directly callback - callback(); - } - return true; -} -#endif // (0 != USB_DEVICE_MAX_EP) - - -#ifdef USB_DEVICE_HS_SUPPORT - -void udd_test_mode_j(void) -{ - udd_enable_hs_test_mode(); - udd_enable_hs_test_mode_j(); -} - - -void udd_test_mode_k(void) -{ - udd_enable_hs_test_mode(); - udd_enable_hs_test_mode_k(); -} - - -void udd_test_mode_se0_nak(void) -{ - udd_enable_hs_test_mode(); -} - - -void udd_test_mode_packet(void) -{ - uint8_t i; - uint8_t *ptr_dest; - const uint8_t *ptr_src; - - const uint8_t test_packet[] = { - // 00000000 * 9 - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - // 01010101 * 8 - 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, - // 01110111 * 8 - 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, - // 0, {111111S * 15}, 111111 - 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, - // S, 111111S, {0111111S * 7} - 0x7F, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD, - // 00111111, {S0111111 * 9}, S0 - 0xFC, 0x7E, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD, 0x7E - }; - - // Reconfigure control endpoint to bulk IN endpoint - udd_disable_endpoint(0); - udd_configure_endpoint(0, USB_EP_TYPE_BULK, 1, - 64, UOTGHS_DEVEPTCFG_EPBK_1_BANK); - udd_allocate_memory(0); - udd_enable_endpoint(0); - - udd_enable_hs_test_mode(); - udd_enable_hs_test_mode_packet(); - - // Send packet on endpoint 0 - ptr_dest = (uint8_t *) & udd_get_endpoint_fifo_access(0, 8); - ptr_src = test_packet; - - for (i = 0; i < sizeof(test_packet); i++) { - *ptr_dest++ = *ptr_src++; - } - udd_ack_fifocon(0); -} -#endif // USB_DEVICE_HS_SUPPORT - - - -//-------------------------------------------------------- -//--- INTERNAL ROUTINES TO MANAGED THE CONTROL ENDPOINT - -static void udd_reset_ep_ctrl(void) -{ - irqflags_t flags; - - // Reset USB address to 0 - udd_configure_address(0); - udd_enable_address(); - - // Alloc and configure control endpoint - udd_configure_endpoint(0, - USB_EP_TYPE_CONTROL, - 0, - USB_DEVICE_EP_CTRL_SIZE, - UOTGHS_DEVEPTCFG_EPBK_1_BANK); - - udd_allocate_memory(0); - udd_enable_endpoint(0); - flags = cpu_irq_save(); - udd_enable_setup_received_interrupt(0); - udd_enable_out_received_interrupt(0); - udd_enable_endpoint_interrupt(0); - cpu_irq_restore(flags); -} - -static void udd_ctrl_init(void) -{ - irqflags_t flags; - flags = cpu_irq_save(); - - // In case of abort of IN Data Phase: - // No need to abort IN transfer (rise TXINI), - // because it is automatically done by hardware when a Setup packet is received. - // But the interrupt must be disabled to don't generate interrupt TXINI - // after SETUP reception. - udd_disable_in_send_interrupt(0); - cpu_irq_restore(flags); - - // In case of OUT ZLP event is no processed before Setup event occurs - udd_ack_out_received(0); - - udd_g_ctrlreq.callback = NULL; - udd_g_ctrlreq.over_under_run = NULL; - udd_g_ctrlreq.payload_size = 0; - udd_ep_control_state = UDD_EPCTRL_SETUP; -} - - -static void udd_ctrl_setup_received(void) -{ - irqflags_t flags; - uint8_t i; - - if (UDD_EPCTRL_SETUP != udd_ep_control_state) { - // May be a hidden DATA or ZLP phase or protocol abort - udd_ctrl_endofrequest(); - - // Reinitializes control endpoint management - udd_ctrl_init(); - } - // Fill setup request structure - if (8 != udd_byte_count(0)) { - udd_ctrl_stall_data(); - udd_ack_setup_received(0); - return; // Error data number doesn't correspond to SETUP packet - } - uint8_t *ptr = (uint8_t *) & udd_get_endpoint_fifo_access(0,8); - for (i = 0; i < 8; i++) { - ((uint8_t*) &udd_g_ctrlreq.req)[i] = *ptr++; - } - // Manage LSB/MSB to fit with CPU usage - udd_g_ctrlreq.req.wValue = le16_to_cpu(udd_g_ctrlreq.req.wValue); - udd_g_ctrlreq.req.wIndex = le16_to_cpu(udd_g_ctrlreq.req.wIndex); - udd_g_ctrlreq.req.wLength = le16_to_cpu(udd_g_ctrlreq.req.wLength); - - // Decode setup request - if (udc_process_setup() == false) { - // Setup request unknow then stall it - udd_ctrl_stall_data(); - udd_ack_setup_received(0); - return; - } - udd_ack_setup_received(0); - - if (Udd_setup_is_in()) { - // IN data phase requested - udd_ctrl_prev_payload_buf_cnt = 0; - udd_ctrl_payload_buf_cnt = 0; - udd_ep_control_state = UDD_EPCTRL_DATA_IN; - udd_ctrl_in_sent(); // Send first data transfer - } else { - if (0 == udd_g_ctrlreq.req.wLength) { - // No data phase requested - // Send IN ZLP to ACK setup request - udd_ctrl_send_zlp_in(); - return; - } - // OUT data phase requested - udd_ctrl_prev_payload_buf_cnt = 0; - udd_ctrl_payload_buf_cnt = 0; - udd_ep_control_state = UDD_EPCTRL_DATA_OUT; - // To detect a protocol error, enable nak interrupt on data IN phase - udd_ack_nak_in(0); - flags = cpu_irq_save(); - udd_enable_nak_in_interrupt(0); - cpu_irq_restore(flags); - } -} - - -static void udd_ctrl_in_sent(void) -{ - static bool b_shortpacket = false; - uint16_t nb_remain; - uint8_t i; - uint8_t *ptr_dest, *ptr_src; - irqflags_t flags; - - flags = cpu_irq_save(); - udd_disable_in_send_interrupt(0); - cpu_irq_restore(flags); - - if (UDD_EPCTRL_HANDSHAKE_WAIT_IN_ZLP == udd_ep_control_state) { - // ZLP on IN is sent, then valid end of setup request - udd_ctrl_endofrequest(); - // Reinitializes control endpoint management - udd_ctrl_init(); - return; - } - Assert(udd_ep_control_state == UDD_EPCTRL_DATA_IN); - - nb_remain = udd_g_ctrlreq.payload_size - udd_ctrl_payload_buf_cnt; - if (0 == nb_remain) { - // All content of current buffer payload are sent - // Update number of total data sending by previous playlaod buffer - udd_ctrl_prev_payload_buf_cnt += udd_ctrl_payload_buf_cnt; - if ((udd_g_ctrlreq.req.wLength == udd_ctrl_prev_payload_buf_cnt) - || b_shortpacket) { - // All data requested are transfered or a short packet has been sent - // then it is the end of data phase. - // Generate an OUT ZLP for handshake phase. - udd_ctrl_send_zlp_out(); - return; - } - // Need of new buffer because the data phase is not complete - if ((!udd_g_ctrlreq.over_under_run) - || (!udd_g_ctrlreq.over_under_run())) { - // Underrun then send zlp on IN - // Here nb_remain=0 and allows to send a IN ZLP - } else { - // A new payload buffer is given - udd_ctrl_payload_buf_cnt = 0; - nb_remain = udd_g_ctrlreq.payload_size; - } - } - // Continue transfer and send next data - if (nb_remain >= USB_DEVICE_EP_CTRL_SIZE) { - nb_remain = USB_DEVICE_EP_CTRL_SIZE; - b_shortpacket = false; - } else { - b_shortpacket = true; - } - // Fill buffer of endpoint control - ptr_dest = (uint8_t *) & udd_get_endpoint_fifo_access(0, 8); - ptr_src = udd_g_ctrlreq.payload + udd_ctrl_payload_buf_cnt; - // Critical section - // Only in case of DATA IN phase abort without USB Reset signal after. - // The IN data don't must be written in endpoint 0 DPRAM during - // a next setup reception in same endpoint 0 DPRAM. - // Thereby, an OUT ZLP reception must check before IN data write - // and if no OUT ZLP is recevied the data must be written quickly (800us) - // before an eventually ZLP OUT and SETUP reception - flags = cpu_irq_save(); - if (Is_udd_out_received(0)) { - // IN DATA phase aborted by OUT ZLP - cpu_irq_restore(flags); - udd_ep_control_state = UDD_EPCTRL_HANDSHAKE_WAIT_OUT_ZLP; - return; // Exit of IN DATA phase - } - // Write quickly the IN data - for (i = 0; i < nb_remain; i++) { - *ptr_dest++ = *ptr_src++; - } - udd_ctrl_payload_buf_cnt += nb_remain; - - // Validate and send the data available in the control endpoint buffer - udd_ack_in_send(0); - udd_enable_in_send_interrupt(0); - // In case of abort of DATA IN phase, no need to enable nak OUT interrupt - // because OUT endpoint is already free and ZLP OUT accepted. - cpu_irq_restore(flags); -} - - -static void udd_ctrl_out_received(void) -{ - irqflags_t flags; - uint8_t i; - uint16_t nb_data; - - if (UDD_EPCTRL_DATA_OUT != udd_ep_control_state) { - if ((UDD_EPCTRL_DATA_IN == udd_ep_control_state) - || (UDD_EPCTRL_HANDSHAKE_WAIT_OUT_ZLP == - udd_ep_control_state)) { - // End of SETUP request: - // - Data IN Phase aborted, - // - or last Data IN Phase hidden by ZLP OUT sending quiclky, - // - or ZLP OUT received normaly. - udd_ctrl_endofrequest(); - } else { - // Protocol error during SETUP request - udd_ctrl_stall_data(); - } - // Reinitializes control endpoint management - udd_ctrl_init(); - return; - } - // Read data received during OUT phase - nb_data = udd_byte_count(0); - if (udd_g_ctrlreq.payload_size < (udd_ctrl_payload_buf_cnt + nb_data)) { - // Payload buffer too small - nb_data = udd_g_ctrlreq.payload_size - udd_ctrl_payload_buf_cnt; - } - uint8_t *ptr_src = (uint8_t *) & udd_get_endpoint_fifo_access(0, 8); - uint8_t *ptr_dest = udd_g_ctrlreq.payload + udd_ctrl_payload_buf_cnt; - for (i = 0; i < nb_data; i++) { - *ptr_dest++ = *ptr_src++; - } - udd_ctrl_payload_buf_cnt += nb_data; - - if ((USB_DEVICE_EP_CTRL_SIZE != nb_data) - || (udd_g_ctrlreq.req.wLength <= - (udd_ctrl_prev_payload_buf_cnt + - udd_ctrl_payload_buf_cnt))) { - // End of reception because it is a short packet - // Before send ZLP, call intermediat calback - // in case of data receiv generate a stall - udd_g_ctrlreq.payload_size = udd_ctrl_payload_buf_cnt; - if (NULL != udd_g_ctrlreq.over_under_run) { - if (!udd_g_ctrlreq.over_under_run()) { - // Stall ZLP - udd_ctrl_stall_data(); - // Ack reception of OUT to replace NAK by a STALL - udd_ack_out_received(0); - return; - } - } - // Send IN ZLP to ACK setup request - udd_ack_out_received(0); - udd_ctrl_send_zlp_in(); - return; - } - - if (udd_g_ctrlreq.payload_size == udd_ctrl_payload_buf_cnt) { - // Overrun then request a new payload buffer - if (!udd_g_ctrlreq.over_under_run) { - // No callback availabled to request a new payload buffer - udd_ctrl_stall_data(); - // Ack reception of OUT to replace NAK by a STALL - udd_ack_out_received(0); - return; - } - if (!udd_g_ctrlreq.over_under_run()) { - // No new payload buffer delivered - udd_ctrl_stall_data(); - // Ack reception of OUT to replace NAK by a STALL - udd_ack_out_received(0); - return; - } - // New payload buffer available - // Update number of total data received - udd_ctrl_prev_payload_buf_cnt += udd_ctrl_payload_buf_cnt; - // Reinit reception on payload buffer - udd_ctrl_payload_buf_cnt = 0; - } - // Free buffer of control endpoint to authorize next reception - udd_ack_out_received(0); - // To detect a protocol error, enable nak interrupt on data IN phase - udd_ack_nak_in(0); - flags = cpu_irq_save(); - udd_enable_nak_in_interrupt(0); - cpu_irq_restore(flags); -} - - -static void udd_ctrl_underflow(void) -{ - if (Is_udd_out_received(0)) - return; // Underflow ignored if OUT data is received - - if (UDD_EPCTRL_DATA_OUT == udd_ep_control_state) { - // Host want to stop OUT transaction - // then stop to wait OUT data phase and wait IN ZLP handshake - udd_ctrl_send_zlp_in(); - } else if (UDD_EPCTRL_HANDSHAKE_WAIT_OUT_ZLP == udd_ep_control_state) { - // A OUT handshake is waiting by device, - // but host want extra IN data then stall extra IN data - udd_enable_stall_handshake(0); - } -} - - -static void udd_ctrl_overflow(void) -{ - if (Is_udd_in_send(0)) - return; // Overflow ignored if IN data is received - - // The case of UDD_EPCTRL_DATA_IN is not managed - // because the OUT endpoint is already free and OUT ZLP accepted - - if (UDD_EPCTRL_HANDSHAKE_WAIT_IN_ZLP == udd_ep_control_state) { - // A IN handshake is waiting by device, - // but host want extra OUT data then stall extra OUT data - udd_enable_stall_handshake(0); - } -} - - -static void udd_ctrl_stall_data(void) -{ - // Stall all packets on IN & OUT control endpoint - udd_ep_control_state = UDD_EPCTRL_STALL_REQ; - udd_enable_stall_handshake(0); -} - - -static void udd_ctrl_send_zlp_in(void) -{ - irqflags_t flags; - - udd_ep_control_state = UDD_EPCTRL_HANDSHAKE_WAIT_IN_ZLP; - - // Validate and send empty IN packet on control endpoint - flags = cpu_irq_save(); - // Send ZLP on IN endpoint - udd_ack_in_send(0); - udd_enable_in_send_interrupt(0); - // To detect a protocol error, enable nak interrupt on data OUT phase - udd_ack_nak_out(0); - udd_enable_nak_out_interrupt(0); - cpu_irq_restore(flags); -} - - -static void udd_ctrl_send_zlp_out(void) -{ - irqflags_t flags; - - udd_ep_control_state = UDD_EPCTRL_HANDSHAKE_WAIT_OUT_ZLP; - // No action is necessary to accept OUT ZLP - // because the buffer of control endpoint is already free - - // To detect a protocol error, enable nak interrupt on data IN phase - flags = cpu_irq_save(); - udd_ack_nak_in(0); - udd_enable_nak_in_interrupt(0); - cpu_irq_restore(flags); -} - - -static void udd_ctrl_endofrequest(void) -{ - // If a callback is registered then call it - if (udd_g_ctrlreq.callback) { - udd_g_ctrlreq.callback(); - } -} - - -static bool udd_ctrl_interrupt(void) -{ - - if (!Is_udd_endpoint_interrupt(0)) { - return false; // No interrupt events on control endpoint - } - - dbg_print("0: "); - - // By default disable overflow and underflow interrupt - udd_disable_nak_in_interrupt(0); - udd_disable_nak_out_interrupt(0); - - // Search event on control endpoint - if (Is_udd_setup_received(0)) { - dbg_print("stup "); - // SETUP packet received - udd_ctrl_setup_received(); - return true; - } - if (Is_udd_in_send(0) && Is_udd_in_send_interrupt_enabled(0)) { - dbg_print("in "); - // IN packet sent - udd_ctrl_in_sent(); - return true; - } - if (Is_udd_out_received(0)) { - dbg_print("out "); - // OUT packet received - udd_ctrl_out_received(); - return true; - } - if (Is_udd_nak_out(0)) { - dbg_print("nako "); - // Overflow on OUT packet - udd_ack_nak_out(0); - udd_ctrl_overflow(); - return true; - } - if (Is_udd_nak_in(0)) { - dbg_print("naki "); - // Underflow on IN packet - udd_ack_nak_in(0); - udd_ctrl_underflow(); - return true; - } - dbg_print("n%x ", UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], 0)); - return false; -} - - -//-------------------------------------------------------- -//--- INTERNAL ROUTINES TO MANAGED THE BULK/INTERRUPT/ISOCHRONOUS ENDPOINTS - -#if (0 != USB_DEVICE_MAX_EP) - -static void udd_ep_job_table_reset(void) -{ - uint8_t i; - for (i = 0; i < USB_DEVICE_MAX_EP; i++) { - udd_ep_job[i].busy = false; - udd_ep_job[i].stall_requested = false; - } -} - - -static void udd_ep_job_table_kill(void) -{ - uint8_t i; - - // For each endpoint, kill job - for (i = 0; i < USB_DEVICE_MAX_EP; i++) { - udd_ep_finish_job(&udd_ep_job[i], true, i + 1); - } -} - - -static void udd_ep_abort_job(udd_ep_id_t ep) -{ - ep &= USB_EP_ADDR_MASK; - - // Abort job on endpoint - udd_ep_finish_job(&udd_ep_job[ep - 1], true, ep); -} - - -static void udd_ep_finish_job(udd_ep_job_t * ptr_job, bool b_abort, uint8_t ep_num) -{ - if (ptr_job->busy == false) { - return; // No on-going job - } - dbg_print("(JobE%x:%d) ", (ptr_job-udd_ep_job)+1, b_abort); - ptr_job->busy = false; - if (NULL == ptr_job->call_trans) { - return; // No callback linked to job - } - if (Is_udd_endpoint_in(ep_num)) { - ep_num |= USB_EP_DIR_IN; - } - ptr_job->call_trans((b_abort) ? UDD_EP_TRANSFER_ABORT : - UDD_EP_TRANSFER_OK, ptr_job->buf_size, ep_num); -} - -#ifdef UDD_EP_DMA_SUPPORTED -static void udd_ep_trans_done(udd_ep_id_t ep) -{ - uint32_t udd_dma_ctrl = 0; - udd_ep_job_t *ptr_job; - iram_size_t next_trans; - irqflags_t flags; - - // Get job corresponding at endpoint - ptr_job = &udd_ep_job[ep - 1]; - - if (!ptr_job->busy) { - return; // No job is running, then ignore it (system error) - } - - if (ptr_job->buf_cnt != ptr_job->buf_size) { - // Need to send or receiv other data - next_trans = ptr_job->buf_size - ptr_job->buf_cnt; - - if (UDD_ENDPOINT_MAX_TRANS < next_trans) { - // The USB hardware support a maximum - // transfer size of UDD_ENDPOINT_MAX_TRANS Bytes - next_trans = UDD_ENDPOINT_MAX_TRANS; - - // Set 0 to tranfer the maximum - udd_dma_ctrl = UOTGHS_DEVDMACONTROL_BUFF_LENGTH(0); - } else { - udd_dma_ctrl = UOTGHS_DEVDMACONTROL_BUFF_LENGTH(next_trans); - } - if (Is_udd_endpoint_in(ep)) { - if (0 != (next_trans % udd_get_endpoint_size(ep))) { - // Enable short packet option - // else the DMA transfer is accepted - // and interrupt DMA valid but nothing is sent. - udd_dma_ctrl |= UOTGHS_DEVDMACONTROL_END_B_EN; - // No need to request another ZLP - ptr_job->b_shortpacket = false; - } - } else { - if ((USB_EP_TYPE_ISOCHRONOUS != udd_get_endpoint_type(ep)) - || (next_trans <= (iram_size_t) udd_get_endpoint_size(ep))) { - - // Enable short packet reception - udd_dma_ctrl |= UOTGHS_DEVDMACONTROL_END_TR_IT - | UOTGHS_DEVDMACONTROL_END_TR_EN; - } - } - - // Start USB DMA to fill or read fifo of the selected endpoint - udd_endpoint_dma_set_addr(ep, (uint32_t) & ptr_job->buf[ptr_job->buf_cnt]); - udd_dma_ctrl |= UOTGHS_DEVDMACONTROL_END_BUFFIT | - UOTGHS_DEVDMACONTROL_CHANN_ENB; - - - // Disable IRQs to have a short sequence - // between read of EOT_STA and DMA enable - flags = cpu_irq_save(); - if (!(udd_endpoint_dma_get_status(ep) - & UOTGHS_DEVDMASTATUS_END_TR_ST)) { - dbg_print("dmaS%x ", ep); - udd_endpoint_dma_set_control(ep, udd_dma_ctrl); - ptr_job->buf_cnt += next_trans; - ptr_job->buf_load = next_trans; - udd_enable_endpoint_dma_interrupt(ep); - cpu_irq_restore(flags); - return; - } - cpu_irq_restore(flags); - - // Here a ZLP has been recieved - // and the DMA transfer must be not started. - // It is the end of transfer - ptr_job->buf_size = ptr_job->buf_cnt; - } - if (Is_udd_endpoint_in(ep)) { - if (ptr_job->b_shortpacket) { - dbg_print("zlpS%x ", ep); - // Need to send a ZLP (No possible with USB DMA) - // enable interrupt to wait a free bank to sent ZLP - udd_ack_in_send(ep); - if (Is_udd_write_enabled(ep)) { - // Force interrupt in case of ep already free - udd_raise_in_send(ep); - } - udd_enable_in_send_interrupt(ep); - udd_enable_endpoint_interrupt(ep); - return; - } - } - dbg_print("dmaE "); - // Call callback to signal end of transfer - udd_ep_finish_job(ptr_job, false, ep); -} -#endif - -#ifdef UDD_EP_FIFO_SUPPORTED -static void udd_ep_in_sent(udd_ep_id_t ep) -{ - udd_ep_job_t *ptr_job = &udd_ep_job[ep - 1]; - uint8_t *ptr_src = &ptr_job->buf[ptr_job->buf_cnt]; - uint8_t *ptr_dst = (uint8_t *) & udd_get_endpoint_fifo_access(ep, 8); - uint32_t pkt_size = udd_get_endpoint_size(ep); - uint32_t nb_data = 0, i; - uint32_t nb_remain; - irqflags_t flags; - - // All transfer done, including ZLP, Finish Job - if (ptr_job->buf_cnt >= ptr_job->buf_size && !ptr_job->b_shortpacket) { - flags = cpu_irq_save(); - udd_disable_in_send_interrupt(ep); - udd_disable_endpoint_interrupt(ep); - cpu_irq_restore(flags); - - ptr_job->buf_size = ptr_job->buf_cnt; // buf_size is passed to callback as XFR count - udd_ep_finish_job(ptr_job, false, ep); - return; - } else { - // ACK TXINI - udd_ack_in_send(ep); - // Fill FIFO - ptr_dst = (uint8_t *) & udd_get_endpoint_fifo_access(ep, 8); - ptr_src = &ptr_job->buf[ptr_job->buf_cnt]; - nb_remain = ptr_job->buf_size - ptr_job->buf_cnt; - // Fill a bank even if no data (ZLP) - nb_data = min(nb_remain, pkt_size); - // Modify job information - ptr_job->buf_cnt += nb_data; - ptr_job->buf_load = nb_data; - - // Copy buffer to FIFO - for (i = 0; i < nb_data; i++) { - *ptr_dst++ = *ptr_src++; - } - // Switch to next bank - udd_ack_fifocon(ep); - // ZLP? - if (nb_data < pkt_size) { - ptr_job->b_shortpacket = false; - } - } -} - -static void udd_ep_out_received(udd_ep_id_t ep) -{ - udd_ep_job_t *ptr_job = &udd_ep_job[ep - 1]; - uint32_t nb_data = 0, i; - uint32_t nb_remain = ptr_job->buf_size - ptr_job->buf_cnt; - uint32_t pkt_size = udd_get_endpoint_size(ep); - uint8_t *ptr_src = (uint8_t *) & udd_get_endpoint_fifo_access(ep, 8); - uint8_t *ptr_dst = &ptr_job->buf[ptr_job->buf_cnt]; - bool b_full = false, b_short = false; - - // Clear RX OUT - udd_ack_out_received(ep); - - // Read byte count - nb_data = udd_byte_count(ep); - if (nb_data < pkt_size) { - b_short = true; - } - //dbg_print("o%d ", ep); - //dbg_print("%d ", nb_data); - // Copy data if there is - if (nb_data > 0) { - if (nb_data >= nb_remain) { - nb_data = nb_remain; - b_full = true; - } - // Modify job information - ptr_job->buf_cnt += nb_data; - ptr_job->buf_load = nb_data; - // Copy FIFO to buffer - for (i = 0; i < nb_data; i++) { - *ptr_dst++ = *ptr_src++; - } - } - // Clear FIFO Status - udd_ack_fifocon(ep); - // Finish job on error or short packet - if (b_full || b_short) { - //dbg_print("EoO%d\n\r", ep); - udd_disable_out_received_interrupt(ep); - udd_disable_endpoint_interrupt(ep); - ptr_job->buf_size = ptr_job->buf_cnt; // buf_size is passed to callback as XFR count - udd_ep_finish_job(ptr_job, false, ep); - } -} -#endif // #ifdef UDD_EP_FIFO_SUPPORTED - -static bool udd_ep_interrupt(void) -{ - udd_ep_id_t ep; - udd_ep_job_t *ptr_job; - - // For each endpoint different of control endpoint (0) - for (ep = 1; ep <= USB_DEVICE_MAX_EP; ep++) { - // Get job corresponding at endpoint - ptr_job = &udd_ep_job[ep - 1]; - -#ifdef UDD_EP_DMA_SUPPORTED - // Check DMA event - if (Is_udd_endpoint_dma_interrupt_enabled(ep) - && Is_udd_endpoint_dma_interrupt(ep)) { - uint32_t nb_remaining; - if (udd_endpoint_dma_get_status(ep) - & UOTGHS_DEVDMASTATUS_CHANN_ENB) { - return true; // Ignore EOT_STA interrupt - } - dbg_print("dma%x: ", ep); - udd_disable_endpoint_dma_interrupt(ep); - // Save number of data no transfered - nb_remaining = (udd_endpoint_dma_get_status(ep) & - UOTGHS_DEVDMASTATUS_BUFF_COUNT_Msk) - >> UOTGHS_DEVDMASTATUS_BUFF_COUNT_Pos; - if (nb_remaining) { - // Transfer no complete (short packet or ZLP) then: - // Update number of data transfered - ptr_job->buf_cnt -= nb_remaining; - // Set transfer complete to stop the transfer - ptr_job->buf_size = ptr_job->buf_cnt; - } - udd_ep_trans_done(ep); - return true; - } -#endif -#ifdef UDD_EP_FIFO_SUPPORTED - // Check RXRDY and TXEMPTY event for none DMA endpoints - if (!Is_udd_endpoint_dma_supported(ep) - && Is_udd_endpoint_interrupt_enabled(ep)) { - dbg_print("ep%x: ", ep); - // RXOUT: Full packet received - if (Is_udd_out_received(ep) - && Is_udd_out_received_interrupt_enabled(ep)) { - dbg_print("Out "); - udd_ep_out_received(ep); - return true; - } - // TXIN: packet sent - if (Is_udd_in_send(ep) - && Is_udd_in_send_interrupt_enabled(ep)) { - dbg_print("In "); - udd_ep_in_sent(ep); - return true; - } - // Errors: Abort? - if (Is_udd_overflow(ep) - || Is_udd_underflow(ep) - || Is_udd_crc_error(ep)) { - dbg_print("Err "); - udd_ep_abort(ep); - return true; - } - } -#endif // UDD_EP_FIFO_SUPPORTED - // Check empty bank interrupt event - if (Is_udd_endpoint_interrupt_enabled(ep)) { - dbg_print("bg%x: ", ep); - if (Is_udd_in_send_interrupt_enabled(ep) - && Is_udd_in_send(ep)) { - dbg_print("I "); - udd_disable_in_send_interrupt(ep); - // One bank is free then send a ZLP - udd_ack_in_send(ep); - udd_ack_fifocon(ep); - udd_ep_finish_job(ptr_job, false, ep); - return true; - } - if (Is_udd_bank_interrupt_enabled(ep) - && (0 == udd_nb_busy_bank(ep))) { - dbg_print("EoT "); - // End of background transfer on IN endpoint - udd_disable_bank_interrupt(ep); - udd_disable_endpoint_interrupt(ep); - - Assert(ptr_job->stall_requested); - // A stall has been requested during backgound transfer - ptr_job->stall_requested = false; - udd_disable_endpoint_bank_autoswitch(ep); - udd_enable_stall_handshake(ep); - udd_reset_data_toggle(ep); - return true; - } - } - } - return false; -} -#endif // (0 != USB_DEVICE_MAX_EP) - -//@} DELETED at91lib/peripherals/uotghs/uotghs_device.h Index: at91lib/peripherals/uotghs/uotghs_device.h ================================================================== --- at91lib/peripherals/uotghs/uotghs_device.h +++ at91lib/peripherals/uotghs/uotghs_device.h @@ -1,661 +0,0 @@ -/** - * \file - * - * \brief USB Device Driver for UOTGHS. Compliant with common UDD driver. - * - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef UOTGHS_DEVICE_H_INCLUDED -#define UOTGHS_DEVICE_H_INCLUDED - -#include "compiler.h" -#include "preprocessor.h" - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/// @endcond - -//! \ingroup udd_group -//! \defgroup udd_udphs_group USB On-The-Go High-Speed Port for device mode (UOTGHS) -//! UOTGHS low-level driver for USB device mode -//! -//! @{ - -#ifndef UOTGHS_DEVEPTCFG_EPDIR_Pos -// Bit pos is not defined in SAM header file but we need it. -# define UOTGHS_DEVEPTCFG_EPDIR_Pos 8 -#endif - -//! @name UOTGHS Device IP properties -//! These macros give access to IP properties -//! @{ - //! Get maximal number of endpoints -#define udd_get_endpoint_max_nbr() (9) -#define UDD_MAX_PEP_NB (udd_get_endpoint_max_nbr() + 1) - //! Get maximal number of banks of endpoints -#define udd_get_endpoint_bank_max_nbr(ep) ((ep == 0) ? 1 : (( ep <= 2) ? 3 : 2)) - //! Get maximal size of endpoint (3X, 1024/64) -#define udd_get_endpoint_size_max(ep) (((ep) == 0) ? 64 : 1024) - //! Get DMA support of endpoints -#define Is_udd_endpoint_dma_supported(ep) ((((ep) >= 1) && ((ep) <= 6)) ? true : false) - //! Get High Band Width support of endpoints -#define Is_udd_endpoint_high_bw_supported(ep) (((ep) >= 2) ? true : false) -//! @} - -//! @name UOTGHS Device speeds management -//! @{ - //! Enable/disable device low-speed mode -#define udd_low_speed_enable() (Set_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_LS)) -#define udd_low_speed_disable() (Clr_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_LS)) - //! Test if device low-speed mode is forced -#define Is_udd_low_speed_enable() (Tst_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_LS)) - -#ifdef UOTGHS_DEVCTRL_SPDCONF_HIGH_SPEED - //! Enable high speed mode -# define udd_high_speed_enable() (Wr_bitfield(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_SPDCONF_Msk, 0)) - //! Disable high speed mode -# define udd_high_speed_disable() (Wr_bitfield(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_SPDCONF_Msk, 3)) - //! Test if controller is in full speed mode -# define Is_udd_full_speed_mode() (Rd_bitfield(UOTGHS->UOTGHS_SR, UOTGHS_SR_SPEED_Msk) == UOTGHS_SR_SPEED_FULL_SPEED) -#else -# define udd_high_speed_enable() do { } while (0) -# define udd_high_speed_disable() do { } while (0) -# define Is_udd_full_speed_mode() true -#endif -//! @} - -//! @name UOTGHS Device HS test mode management -//! @{ -#ifdef UOTGHS_DEVCTRL_SPDCONF_HIGH_SPEED - //! Enable high speed test mode -# define udd_enable_hs_test_mode() (Wr_bitfield(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_SPDCONF_Msk, 2)) -# define udd_enable_hs_test_mode_j() (Set_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_TSTJ)) -# define udd_enable_hs_test_mode_k() (Set_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_TSTK)) -# define udd_enable_hs_test_mode_packet() (Set_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_TSTPCKT)) -#endif -//! @} - -//! @name UOTGHS Device vbus management -//! @{ -#define udd_enable_vbus_interrupt() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBUSTE)) -#define udd_disable_vbus_interrupt() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBUSTE)) -#define Is_udd_vbus_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBUSTE)) -#define Is_udd_vbus_high() (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_VBUS)) -#define Is_udd_vbus_low() (!Is_udd_vbus_high()) -#define udd_ack_vbus_transition() (UOTGHS->UOTGHS_SCR = UOTGHS_SCR_VBUSTIC) -#define udd_raise_vbus_transition() (UOTGHS->UOTGHS_SFR = UOTGHS_SFR_VBUSTIS) -#define Is_udd_vbus_transition() (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_VBUSTI)) -//! @} - - -//! @name UOTGHS device attach control -//! These macros manage the UOTGHS Device attach. -//! @{ - //! Detaches from USB bus -#define udd_detach_device() (Set_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_DETACH)) - //! Attaches to USB bus -#define udd_attach_device() (Clr_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_DETACH)) - //! Test if the device is detached -#define Is_udd_detached() (Tst_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_DETACH)) -//! @} - - -//! @name UOTGHS device bus events control -//! These macros manage the UOTGHS Device bus events. -//! @{ - -//! Initiates a remote wake-up event -//! @{ -#define udd_initiate_remote_wake_up() (Set_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_RMWKUP)) -#define Is_udd_pending_remote_wake_up() (Tst_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_RMWKUP)) -//! @} - -//! Manage upstream resume event (=remote wakeup) -//! The USB driver sends a resume signal called "Upstream Resume" -//! @{ -#define udd_enable_remote_wake_up_interrupt() (UOTGHS->UOTGHS_DEVIER = UOTGHS_DEVIER_UPRSMES) -#define udd_disable_remote_wake_up_interrupt() (UOTGHS->UOTGHS_DEVIDR = UOTGHS_DEVIDR_UPRSMEC) -#define Is_udd_remote_wake_up_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_DEVIMR, UOTGHS_DEVIMR_UPRSME)) -#define udd_ack_remote_wake_up_start() (UOTGHS->UOTGHS_DEVICR = UOTGHS_DEVICR_UPRSMC) -#define udd_raise_remote_wake_up_start() (UOTGHS->UOTGHS_DEVIFR = UOTGHS_DEVIFR_UPRSMS) -#define Is_udd_remote_wake_up_start() (Tst_bits(UOTGHS->UOTGHS_DEVISR, UOTGHS_DEVISR_UPRSM)) -//! @} - -//! Manage downstream resume event (=remote wakeup from host) -//! The USB controller detects a valid "End of Resume" signal initiated by the host -//! @{ -#define udd_enable_resume_interrupt() (UOTGHS->UOTGHS_DEVIER = UOTGHS_DEVIER_EORSMES) -#define udd_disable_resume_interrupt() (UOTGHS->UOTGHS_DEVIDR = UOTGHS_DEVIDR_EORSMEC) -#define Is_udd_resume_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_DEVIMR, UOTGHS_DEVIMR_EORSME)) -#define udd_ack_resume() (UOTGHS->UOTGHS_DEVICR = UOTGHS_DEVICR_EORSMC) -#define udd_raise_resume() (UOTGHS->UOTGHS_DEVIFR = UOTGHS_DEVIFR_EORSMS) -#define Is_udd_resume() (Tst_bits(UOTGHS->UOTGHS_DEVISR, UOTGHS_DEVISR_EORSM)) -//! @} - -//! Manage wake-up event (=usb line activity) -//! The USB controller is reactivated by a filtered non-idle signal from the lines -//! @{ -#define udd_enable_wake_up_interrupt() (UOTGHS->UOTGHS_DEVIER = UOTGHS_DEVIER_WAKEUPES) -#define udd_disable_wake_up_interrupt() (UOTGHS->UOTGHS_DEVIDR = UOTGHS_DEVIDR_WAKEUPEC) -#define Is_udd_wake_up_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_DEVIMR, UOTGHS_DEVIMR_WAKEUPE)) -#define udd_ack_wake_up() (UOTGHS->UOTGHS_DEVICR = UOTGHS_DEVICR_WAKEUPC) -#define udd_raise_wake_up() (UOTGHS->UOTGHS_DEVIFR = UOTGHS_DEVIFR_WAKEUPS) -#define Is_udd_wake_up() (Tst_bits(UOTGHS->UOTGHS_DEVISR, UOTGHS_DEVISR_WAKEUP)) -//! @} - -//! Manage reset event -//! Set when a USB "End of Reset" has been detected -//! @{ -#define udd_enable_reset_interrupt() (UOTGHS->UOTGHS_DEVIER = UOTGHS_DEVIER_EORSTES) -#define udd_disable_reset_interrupt() (UOTGHS->UOTGHS_DEVIDR = UOTGHS_DEVIDR_EORSTEC) -#define Is_udd_reset_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_DEVIMR, UOTGHS_DEVIMR_EORSTE)) -#define udd_ack_reset() (UOTGHS->UOTGHS_DEVICR = UOTGHS_DEVICR_EORSTC) -#define udd_raise_reset() (UOTGHS->UOTGHS_DEVIFR = UOTGHS_DEVIFR_EORSTS) -#define Is_udd_reset() (Tst_bits(UOTGHS->UOTGHS_DEVISR, UOTGHS_DEVISR_EORST)) -//! @} - -//! Manage start of frame event -//! @{ -#define udd_enable_sof_interrupt() (UOTGHS->UOTGHS_DEVIER = UOTGHS_DEVIER_SOFES) -#define udd_disable_sof_interrupt() (UOTGHS->UOTGHS_DEVIDR = UOTGHS_DEVIDR_SOFEC) -#define Is_udd_sof_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_DEVIMR, UOTGHS_DEVIMR_SOFE)) -#define udd_ack_sof() (UOTGHS->UOTGHS_DEVICR = UOTGHS_DEVICR_SOFC) -#define udd_raise_sof() (UOTGHS->UOTGHS_DEVIFR = UOTGHS_DEVIFR_SOFS) -#define Is_udd_sof() (Tst_bits(UOTGHS->UOTGHS_DEVISR, UOTGHS_DEVISR_SOF)) -#define udd_frame_number() (Rd_bitfield(UOTGHS->UOTGHS_DEVFNUM, UOTGHS_DEVFNUM_FNUM_Msk)) -#define Is_udd_frame_number_crc_error() (Tst_bits(UOTGHS->UOTGHS_DEVFNUM, UOTGHS_DEVFNUM_FNCERR)) -//! @} - -//! Manage Micro start of frame event (High Speed Only) -//! @{ -#define udd_enable_msof_interrupt() (UOTGHS->UOTGHS_DEVIER = UOTGHS_DEVIER_MSOFES) -#define udd_disable_msof_interrupt() (UOTGHS->UOTGHS_DEVIDR = UOTGHS_DEVIDR_MSOFEC) -#define Is_udd_msof_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_DEVIMR, UOTGHS_DEVIMR_MSOFE)) -#define udd_ack_msof() (UOTGHS->UOTGHS_DEVICR = UOTGHS_DEVIMR_MSOFE) -#define udd_raise_msof() (UOTGHS->UOTGHS_DEVIFR = UOTGHS_DEVIFR_MSOFS) -#define Is_udd_msof() (Tst_bits(UOTGHS->UOTGHS_DEVISR, UOTGHS_DEVISR_MSOF)) -#define udd_micro_frame_number() \ - (Rd_bitfield(UOTGHS->UOTGHS_DEVFNUM, (UOTGHS_DEVFNUM_FNUM_Msk|UOTGHS_DEVFNUM_MFNUM_Msk))) -//! @} - -//! Manage suspend event -//! @{ -#define udd_enable_suspend_interrupt() (UOTGHS->UOTGHS_DEVIER = UOTGHS_DEVIER_SUSPES) -#define udd_disable_suspend_interrupt() (UOTGHS->UOTGHS_DEVIDR = UOTGHS_DEVIDR_SUSPEC) -#define Is_udd_suspend_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_DEVIMR, UOTGHS_DEVIMR_SUSPE)) -#define udd_ack_suspend() (UOTGHS->UOTGHS_DEVICR = UOTGHS_DEVICR_SUSPC) -#define udd_raise_suspend() (UOTGHS->UOTGHS_DEVIFR = UOTGHS_DEVIFR_SUSPS) -#define Is_udd_suspend() (Tst_bits(UOTGHS->UOTGHS_DEVISR, UOTGHS_DEVISR_SUSP)) -//! @} - -//! @} - -//! @name UOTGHS device address control -//! These macros manage the UOTGHS Device address. -//! @{ - //! enables USB device address -#define udd_enable_address() (Set_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_ADDEN)) - //! disables USB device address -#define udd_disable_address() (Clr_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_ADDEN)) -#define Is_udd_address_enabled() (Tst_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_ADDEN)) - //! configures the USB device address -#define udd_configure_address(addr) (Wr_bitfield(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_UADD_Msk, addr)) - //! gets the currently configured USB device address -#define udd_get_configured_address() (Rd_bitfield(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_UADD_Msk)) -//! @} - - -//! @name UOTGHS Device endpoint drivers -//! These macros manage the common features of the endpoints. -//! @{ - -//! Generic macro for UOTGHS registers that can be arrayed -//! @{ -#define UOTGHS_ARRAY(reg,index) ((&(UOTGHS->reg))[(index)]) -//! @} - -//! @name UOTGHS Device endpoint configuration -//! @{ - //! enables the selected endpoint -#define udd_enable_endpoint(ep) (Set_bits(UOTGHS->UOTGHS_DEVEPT, UOTGHS_DEVEPT_EPEN0 << (ep))) - //! disables the selected endpoint -#define udd_disable_endpoint(ep) (Clr_bits(UOTGHS->UOTGHS_DEVEPT, UOTGHS_DEVEPT_EPEN0 << (ep))) - //! tests if the selected endpoint is enabled -#define Is_udd_endpoint_enabled(ep) (Tst_bits(UOTGHS->UOTGHS_DEVEPT, UOTGHS_DEVEPT_EPEN0 << (ep))) - //! resets the selected endpoint -#define udd_reset_endpoint(ep) \ - do { \ - Set_bits(UOTGHS->UOTGHS_DEVEPT, UOTGHS_DEVEPT_EPRST0 << (ep)); \ - Clr_bits(UOTGHS->UOTGHS_DEVEPT, UOTGHS_DEVEPT_EPRST0 << (ep)); \ - } while (0) - //! Tests if the selected endpoint is being reset -#define Is_udd_resetting_endpoint(ep) (Tst_bits(UOTGHS->UOTGHS_DEVEPT, UOTGHS_DEVEPT_EPRST0 << (ep))) - - //! Configures the selected endpoint type -#define udd_configure_endpoint_type(ep, type) (Wr_bitfield(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_EPTYPE_Msk, type)) - //! Gets the configured selected endpoint type -#define udd_get_endpoint_type(ep) (Rd_bitfield(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_EPTYPE_Msk)) - //! Enables the bank autoswitch for the selected endpoint -#define udd_enable_endpoint_bank_autoswitch(ep) (Set_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_AUTOSW)) - //! Disables the bank autoswitch for the selected endpoint -#define udd_disable_endpoint_bank_autoswitch(ep) (Clr_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_AUTOSW)) -#define Is_udd_endpoint_bank_autoswitch_enabled(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_AUTOSW)) - //! Configures the selected endpoint direction -#define udd_configure_endpoint_direction(ep, dir) (Wr_bitfield(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_EPDIR, dir)) - //! Gets the configured selected endpoint direction -#define udd_get_endpoint_direction(ep) (Rd_bitfield(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_EPDIR)) -#define Is_udd_endpoint_in(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_EPDIR)) - //! Bounds given integer size to allowed range and rounds it up to the nearest - //! available greater size, then applies register format of UOTGHS controller - //! for endpoint size bit-field. -#define udd_format_endpoint_size(size) (32 - clz(((uint32_t)min(max(size, 8), 1024) << 1) - 1) - 1 - 3) - //! Configures the selected endpoint size -#define udd_configure_endpoint_size(ep, size) (Wr_bitfield(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_EPSIZE_Msk, udd_format_endpoint_size(size))) - //! Gets the configured selected endpoint size -#define udd_get_endpoint_size(ep) (8 << Rd_bitfield(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_EPSIZE_Msk)) - //! Configures the selected endpoint number of banks -#define udd_configure_endpoint_bank(ep, bank) (Wr_bitfield(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_EPBK_Msk, bank)) - //! Gets the configured selected endpoint number of banks -#define udd_get_endpoint_bank(ep) (Rd_bitfield(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_EPBK_Msk)+1) - //! Allocates the configuration selected endpoint in DPRAM memory -#define udd_allocate_memory(ep) (Set_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_ALLOC)) - //! un-allocates the configuration selected endpoint in DPRAM memory -#define udd_unallocate_memory(ep) (Clr_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_ALLOC)) -#define Is_udd_memory_allocated(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_ALLOC)) - - //! Configures selected endpoint in one step -#define udd_configure_endpoint(ep, type, dir, size, bank) (\ - Wr_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_EPTYPE_Msk |\ - UOTGHS_DEVEPTCFG_EPDIR |\ - UOTGHS_DEVEPTCFG_EPSIZE_Msk |\ - UOTGHS_DEVEPTCFG_EPBK_Msk , \ - (((uint32_t)(type) << UOTGHS_DEVEPTCFG_EPTYPE_Pos) & UOTGHS_DEVEPTCFG_EPTYPE_Msk) |\ - (((uint32_t)(dir ) << UOTGHS_DEVEPTCFG_EPDIR_Pos ) & UOTGHS_DEVEPTCFG_EPDIR) |\ - ( (uint32_t)udd_format_endpoint_size(size) << UOTGHS_DEVEPTCFG_EPSIZE_Pos) |\ - (((uint32_t)(bank) << UOTGHS_DEVEPTCFG_EPBK_Pos) & UOTGHS_DEVEPTCFG_EPBK_Msk))\ -) - //! Tests if current endpoint is configured -#define Is_udd_endpoint_configured(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_CFGOK)) - //! Returns the control direction -#define udd_control_direction() (Rd_bitfield(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], EP_CONTROL), UOTGHS_DEVEPTISR_CTRLDIR)) - - //! Resets the data toggle sequence -#define udd_reset_data_toggle(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIER[0], ep) = UOTGHS_DEVEPTIER_RSTDTS) - //! Tests if the data toggle sequence is being reset -#define Is_udd_data_toggle_reset(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_RSTDT)) - //! Returns data toggle -#define udd_data_toggle(ep) (Rd_bitfield(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_DTSEQ_Msk)) -//! @} - - -//! @name UOTGHS Device control endpoint -//! These macros control the endpoints. -//! @{ - -//! @name UOTGHS Device control endpoint interrupts -//! These macros control the endpoints interrupts. -//! @{ - //! Enables the selected endpoint interrupt -#define udd_enable_endpoint_interrupt(ep) (UOTGHS->UOTGHS_DEVIER = UOTGHS_DEVIER_PEP_0 << (ep)) - //! Disables the selected endpoint interrupt -#define udd_disable_endpoint_interrupt(ep) (UOTGHS->UOTGHS_DEVIDR = UOTGHS_DEVIDR_PEP_0 << (ep)) - //! Tests if the selected endpoint interrupt is enabled -#define Is_udd_endpoint_interrupt_enabled(ep) (Tst_bits(UOTGHS->UOTGHS_DEVIMR, UOTGHS_DEVIMR_PEP_0 << (ep))) - //! Tests if an interrupt is triggered by the selected endpoint -#define Is_udd_endpoint_interrupt(ep) (Tst_bits(UOTGHS->UOTGHS_DEVISR, UOTGHS_DEVISR_PEP_0 << (ep))) - //! Returns the lowest endpoint number generating an endpoint interrupt or MAX_PEP_NB if none -#define udd_get_interrupt_endpoint_number() (ctz(((UOTGHS->UOTGHS_DEVISR >> UOTGHS_DEVISR_PEP_Pos) & \ - (UOTGHS->UOTGHS_DEVIMR >> UOTGHS_DEVIMR_PEP_Pos)) | \ - (1 << MAX_PEP_NB))) -#define UOTGHS_DEVISR_PEP_Pos 12 -#define UOTGHS_DEVIMR_PEP_Pos 12 -//! @} - -//! @name UOTGHS Device control endpoint errors -//! These macros control the endpoint errors. -//! @{ - //! Enables the STALL handshake -#define udd_enable_stall_handshake(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIER[0], ep) = UOTGHS_DEVEPTIER_STALLRQS) - //! Disables the STALL handshake -#define udd_disable_stall_handshake(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIDR[0], ep) = UOTGHS_DEVEPTIDR_STALLRQC) - //! Tests if STALL handshake request is running -#define Is_udd_endpoint_stall_requested(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_STALLRQ)) - //! Tests if STALL sent -#define Is_udd_stall(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_STALLEDI)) - //! ACKs STALL sent -#define udd_ack_stall(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTICR[0], ep) = UOTGHS_DEVEPTICR_STALLEDIC) - //! Raises STALL sent -#define udd_raise_stall(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIFR[0], ep) = UOTGHS_DEVEPTIFR_STALLEDIS) - //! Enables STALL sent interrupt -#define udd_enable_stall_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIER[0], ep) = UOTGHS_DEVEPTIER_STALLEDES) - //! Disables STALL sent interrupt -#define udd_disable_stall_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIDR[0], ep) = UOTGHS_DEVEPTIDR_STALLEDEC) - //! Tests if STALL sent interrupt is enabled -#define Is_udd_stall_interrupt_enabled(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_STALLEDE)) - - //! Tests if NAK OUT received -#define Is_udd_nak_out(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_NAKOUTI)) - //! ACKs NAK OUT received -#define udd_ack_nak_out(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTICR[0], ep) = UOTGHS_DEVEPTICR_NAKOUTIC) - //! Raises NAK OUT received -#define udd_raise_nak_out(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIFR[0], ep) = UOTGHS_DEVEPTIFR_NAKOUTIS) - //! Enables NAK OUT interrupt -#define udd_enable_nak_out_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIER[0], ep) = UOTGHS_DEVEPTIER_NAKOUTES) - //! Disables NAK OUT interrupt -#define udd_disable_nak_out_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIDR[0], ep) = UOTGHS_DEVEPTIDR_NAKOUTEC) - //! Tests if NAK OUT interrupt is enabled -#define Is_udd_nak_out_interrupt_enabled(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_NAKOUTE)) - - //! Tests if NAK IN received -#define Is_udd_nak_in(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_NAKINI)) - //! ACKs NAK IN received -#define udd_ack_nak_in(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTICR[0], ep) = UOTGHS_DEVEPTICR_NAKINIC) - //! Raises NAK IN received -#define udd_raise_nak_in(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIFR[0], ep) = UOTGHS_DEVEPTIFR_NAKINIS) - //! Enables NAK IN interrupt -#define udd_enable_nak_in_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIER[0], ep) = UOTGHS_DEVEPTIER_NAKINES) - //! Disables NAK IN interrupt -#define udd_disable_nak_in_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIDR[0], ep) = UOTGHS_DEVEPTIDR_NAKINEC) - //! Tests if NAK IN interrupt is enabled -#define Is_udd_nak_in_interrupt_enabled(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_NAKINE)) - - //! ACKs endpoint isochronous overflow interrupt -#define udd_ack_overflow_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTICR[0], ep) = UOTGHS_DEVEPTICR_OVERFIC) - //! Raises endpoint isochronous overflow interrupt -#define udd_raise_overflow_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIFR[0], ep) = UOTGHS_DEVEPTIFR_OVERFIS) - //! Tests if an overflow occurs -#define Is_udd_overflow(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_OVERFI)) - //! Enables overflow interrupt -#define udd_enable_overflow_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIER[0], ep) = UOTGHS_DEVEPTIER_OVERFES) - //! Disables overflow interrupt -#define udd_disable_overflow_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIDR[0], ep) = UOTGHS_DEVEPTIDR_OVERFEC) - //! Tests if overflow interrupt is enabled -#define Is_udd_overflow_interrupt_enabled(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_OVERFE)) - - //! ACKs endpoint isochronous underflow interrupt -#define udd_ack_underflow_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTICR[0], ep) = UOTGHS_DEVEPTICR_UNDERFIC) - //! Raises endpoint isochronous underflow interrupt -#define udd_raise_underflow_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIFR[0], ep) = UOTGHS_DEVEPTIFR_UNDERFIS) - //! Tests if an underflow occurs -#define Is_udd_underflow(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_UNDERFI)) - //! Enables underflow interrupt -#define udd_enable_underflow_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIER[0], ep) = UOTGHS_DEVEPTIER_UNDERFES) - //! Disables underflow interrupt -#define udd_disable_underflow_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIDR[0], ep) = UOTGHS_DEVEPTIDR_UNDERFEC) - //! Tests if underflow interrupt is enabled -#define Is_udd_underflow_interrupt_enabled(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_UNDERFE)) - - //! Tests if CRC ERROR ISO OUT detected -#define Is_udd_crc_error(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_CRCERRI)) - //! ACKs CRC ERROR ISO OUT detected -#define udd_ack_crc_error(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTICR[0], ep) = UOTGHS_DEVEPTICR_CRCERRIC) - //! Raises CRC ERROR ISO OUT detected -#define udd_raise_crc_error(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIFR[0], ep) = UOTGHS_DEVEPTIFR_CRCERRIS) - //! Enables CRC ERROR ISO OUT detected interrupt -#define udd_enable_crc_error_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIER[0], ep) = UOTGHS_DEVEPTIER_CRCERRES) - //! Disables CRC ERROR ISO OUT detected interrupt -#define udd_disable_crc_error_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIDR[0], ep) = UOTGHS_DEVEPTIDR_CRCERREC) - //! Tests if CRC ERROR ISO OUT detected interrupt is enabled -#define Is_udd_crc_error_interrupt_enabled(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_CRCERRE)) -//! @} - -//! @name UOTGHS Device control endpoint transfer -//! These macros control the endpoint transfer. -//! @{ - - //! Tests if endpoint read allowed -#define Is_udd_read_enabled(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_RWALL)) - //! Tests if endpoint write allowed -#define Is_udd_write_enabled(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_RWALL)) - - //! Returns the byte count -#define udd_byte_count(ep) (Rd_bitfield(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_BYCT_Msk)) - //! Clears FIFOCON bit -#define udd_ack_fifocon(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIDR[0], ep) = UOTGHS_DEVEPTIDR_FIFOCONC) - //! Tests if FIFOCON bit set -#define Is_udd_fifocon(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_FIFOCON)) - - //! Returns the number of busy banks -#define udd_nb_busy_bank(ep) (Rd_bitfield(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_NBUSYBK_Msk)) - //! Returns the number of the current bank -#define udd_current_bank(ep) (Rd_bitfield(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_CURRBK_Msk)) - //! Kills last bank -#define udd_kill_last_in_bank(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIER[0], ep) = UOTGHS_DEVEPTIER_KILLBKS) -#define Is_udd_kill_last(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_KILLBK)) - //! Tests if last bank killed -#define Is_udd_last_in_bank_killed(ep) (!Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_KILLBK)) - //! Forces all banks full (OUT) or free (IN) interrupt -#define udd_force_bank_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIFR[0], ep) = UOTGHS_DEVEPTIFR_NBUSYBKS) - //! Unforces all banks full (OUT) or free (IN) interrupt -#define udd_unforce_bank_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIFR[0], ep) = UOTGHS_DEVEPTIFR_NBUSYBKS) - //! Enables all banks full (OUT) or free (IN) interrupt -#define udd_enable_bank_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIER[0], ep) = UOTGHS_DEVEPTIER_NBUSYBKES) - //! Disables all banks full (OUT) or free (IN) interrupt -#define udd_disable_bank_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIDR[0], ep) = UOTGHS_DEVEPTIDR_NBUSYBKEC) - //! Tests if all banks full (OUT) or free (IN) interrupt enabled -#define Is_udd_bank_interrupt_enabled(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_NBUSYBKE)) - - //! Tests if SHORT PACKET received -#define Is_udd_short_packet(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_SHORTPACKET)) - //! ACKs SHORT PACKET received -#define udd_ack_short_packet(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTICR[0], ep) = UOTGHS_DEVEPTICR_SHORTPACKETC) - //! Raises SHORT PACKET received -#define udd_raise_short_packet(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIFR[0], ep) = UOTGHS_DEVEPTIFR_SHORTPACKETS) - //! Enables SHORT PACKET received interrupt -#define udd_enable_short_packet_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIER[0], ep) = UOTGHS_DEVEPTIER_SHORTPACKETES) - //! Disables SHORT PACKET received interrupt -#define udd_disable_short_packet_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIDR[0], ep) = UOTGHS_DEVEPTIDR_SHORTPACKETEC) - //! Tests if SHORT PACKET received interrupt is enabled -#define Is_udd_short_packet_interrupt_enabled(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_SHORTPACKETE)) - - //! Tests if SETUP received -#define Is_udd_setup_received(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_RXSTPI)) - //! ACKs SETUP received -#define udd_ack_setup_received(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTICR[0], ep) = UOTGHS_DEVEPTICR_RXSTPIC) - //! Raises SETUP received -#define udd_raise_setup_received(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIFR[0], ep) = UOTGHS_DEVEPTIFR_RXSTPIS) - //! Enables SETUP received interrupt -#define udd_enable_setup_received_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIER[0], ep) = UOTGHS_DEVEPTIER_RXSTPES) - //! Disables SETUP received interrupt -#define udd_disable_setup_received_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIDR[0], ep) = UOTGHS_DEVEPTIDR_RXSTPEC) - //! Tests if SETUP received interrupt is enabled -#define Is_udd_setup_received_interrupt_enabled(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_RXSTPE)) - - //! Tests if OUT received -#define Is_udd_out_received(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_RXOUTI)) - //! ACKs OUT received -#define udd_ack_out_received(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTICR[0], ep) = UOTGHS_DEVEPTICR_RXOUTIC) - //! Raises OUT received -#define udd_raise_out_received(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIFR[0], ep) = UOTGHS_DEVEPTIFR_RXOUTIS) - //! Enables OUT received interrupt -#define udd_enable_out_received_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIER[0], ep) = UOTGHS_DEVEPTIER_RXOUTES) - //! Disables OUT received interrupt -#define udd_disable_out_received_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIDR[0], ep) = UOTGHS_DEVEPTIDR_RXOUTEC) - //! Tests if OUT received interrupt is enabled -#define Is_udd_out_received_interrupt_enabled(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_RXOUTE)) - - //! Tests if IN sending -#define Is_udd_in_send(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_TXINI)) - //! ACKs IN sending -#define udd_ack_in_send(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTICR[0], ep) = UOTGHS_DEVEPTICR_TXINIC) - //! Raises IN sending -#define udd_raise_in_send(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIFR[0], ep) = UOTGHS_DEVEPTIFR_TXINIS) - //! Enables IN sending interrupt -#define udd_enable_in_send_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIER[0], ep) = UOTGHS_DEVEPTIER_TXINES) - //! Disables IN sending interrupt -#define udd_disable_in_send_interrupt(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIDR[0], ep) = UOTGHS_DEVEPTIDR_TXINEC) - //! Tests if IN sending interrupt is enabled -#define Is_udd_in_send_interrupt_enabled(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_TXINE)) - - - //! Get 64-, 32-, 16- or 8-bit access to FIFO data register of selected endpoint. - //! @param ep Endpoint of which to access FIFO data register - //! @param scale Data scale in bits: 64, 32, 16 or 8 - //! @return Volatile 64-, 32-, 16- or 8-bit data pointer to FIFO data register - //! @warning It is up to the user of this macro to make sure that all accesses - //! are aligned with their natural boundaries except 64-bit accesses which - //! require only 32-bit alignment. - //! @warning It is up to the user of this macro to make sure that used HSB - //! addresses are identical to the DPRAM internal pointer modulo 32 bits. -#define udd_get_endpoint_fifo_access(ep, scale) \ - (((volatile TPASTE2(U, scale) (*)[0x8000 / ((scale) / 8)])UOTGHS_RAM_ADDR)[(ep)]) - -//! @name UOTGHS endpoint DMA drivers -//! These macros manage the common features of the endpoint DMA channels. -//! @{ - - //! Maximum transfer size on USB DMA -#define UDD_ENDPOINT_MAX_TRANS 0x10000 - //! Enables the disabling of HDMA requests by endpoint interrupts -#define udd_enable_endpoint_int_dis_hdma_req(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIER[0](ep) = UOTGHS_DEVEPTIER_EPDISHDMAS) - //! Disables the disabling of HDMA requests by endpoint interrupts -#define udd_disable_endpoint_int_dis_hdma_req(ep) (UOTGHS_ARRAY(UOTGHS_DEVEPTIDR[0](ep) = UOTGHS_DEVEPTIDR_EPDISHDMAC) - //! Tests if the disabling of HDMA requests by endpoint interrupts is enabled -#define Is_udd_endpoint_int_dis_hdma_req_enabled(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0](ep), UOTGHS_DEVEPTIMR_EPDISHDMA)) - - //! Raises the selected endpoint DMA channel interrupt -#define udd_raise_endpoint_dma_interrupt(ep) (UOTGHS->UOTGHS_DEVIFR = UOTGHS_DEVIFR_DMA_1 << ((ep) - 1)) - //! Raises the selected endpoint DMA channel interrupt -#define udd_clear_endpoint_dma_interrupt(ep) (UOTGHS->UOTGHS_DEVICR = UOTGHS_DEVISR_DMA_1 << ((ep) - 1)) - //! Tests if an interrupt is triggered by the selected endpoint DMA channel -#define Is_udd_endpoint_dma_interrupt(ep) (Tst_bits(UOTGHS->UOTGHS_DEVISR, UOTGHS_DEVISR_DMA_1 << ((ep) - 1))) - //! Enables the selected endpoint DMA channel interrupt -#define udd_enable_endpoint_dma_interrupt(ep) (UOTGHS->UOTGHS_DEVIER = UOTGHS_DEVIER_DMA_1 << ((ep) - 1)) - //! Disables the selected endpoint DMA channel interrupt -#define udd_disable_endpoint_dma_interrupt(ep) (UOTGHS->UOTGHS_DEVIDR = UOTGHS_DEVIDR_DMA_1 << ((ep) - 1)) - //! Tests if the selected endpoint DMA channel interrupt is enabled -#define Is_udd_endpoint_dma_interrupt_enabled(ep) (Tst_bits(UOTGHS->UOTGHS_DEVIMR, UOTGHS_DEVIMR_DMA_1 << ((ep) - 1))) - - //! Access points to the UOTGHS device DMA memory map with arrayed registers - //! @{ - //! Structure for DMA next descriptor register -typedef struct { - uint32_t *NXT_DSC_ADD; -} uotghs_dma_nextdesc_t; - //! Structure for DMA control register -typedef struct { - uint32_t CHANN_ENB:1, - LDNXT_DSC:1, - END_TR_EN:1, - END_B_EN:1, - END_TR_IT:1, - END_BUFFIT:1, - DESC_LD_IT:1, - BUST_LCK:1, - reserved:8, - BUFF_LENGTH:16; -} uotghs_dma_control_t; - //! Structure for DMA status register -typedef struct { - uint32_t CHANN_ENB:1, - CHANN_ACT:1, - reserved0:2, - END_TR_ST:1, - END_BF_ST:1, - DESC_LDST:1, - reserved1:9, - BUFF_COUNT:16; -} uotghs_dma_status_t; - //! Structure for DMA descriptor -typedef struct { - union { - uint32_t nextdesc; - uotghs_dma_nextdesc_t NEXTDESC; - }; - uint32_t addr; - union { - uint32_t control; - uotghs_dma_control_t CONTROL; - }; - uint32_t reserved; -} sam_uotghs_dmadesc_t, uotghs_dmadesc_t; - //! Structure for DMA registers in a channel -typedef struct { - union { - uint32_t nextdesc; - uotghs_dma_nextdesc_t NEXTDESC; - }; - uint32_t addr; - union { - uint32_t control; - uotghs_dma_control_t CONTROL; - }; - union { - unsigned long status; - uotghs_dma_status_t STATUS; - }; -} sam_uotghs_dmach_t, uotghs_dmach_t; - //! DMA channel control command -#define UDD_ENDPOINT_DMA_STOP_NOW (0) -#define UDD_ENDPOINT_DMA_RUN_AND_STOP (UOTGHS_DEVDMACONTROL_CHANN_ENB) -#define UDD_ENDPOINT_DMA_LOAD_NEXT_DESC (UOTGHS_DEVDMACONTROL_LDNXT_DSC) -#define UDD_ENDPOINT_DMA_RUN_AND_LINK (UOTGHS_DEVDMACONTROL_CHANN_ENB|UOTGHS_DEVDMACONTROL_LDNXT_DSC) - //! Structure for DMA registers -#define UOTGHS_UDDMA_ARRAY(ep) (((volatile uotghs_dmach_t *)UOTGHS->UOTGHS_DEVDMA)[(ep) - 1]) - - //! Set control desc to selected endpoint DMA channel -#define udd_endpoint_dma_set_control(ep,desc) (UOTGHS_UDDMA_ARRAY(ep).control = desc) - //! Get control desc to selected endpoint DMA channel -#define udd_endpoint_dma_get_control(ep) (UOTGHS_UDDMA_ARRAY(ep).control) - //! Set RAM address to selected endpoint DMA channel -#define udd_endpoint_dma_set_addr(ep,add) (UOTGHS_UDDMA_ARRAY(ep).addr = add) - //! Get status to selected endpoint DMA channel -#define udd_endpoint_dma_get_status(ep) (UOTGHS_UDDMA_ARRAY(ep).status) - //! @} -//! @} - -//! @} -//! @} -//! @} -//! @} - - -/// @cond 0 -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/// @endcond - -#endif /* UOTGHS_DEVICE_H_INCLUDED */ DELETED at91lib/peripherals/uotghs/uotghs_otg.h Index: at91lib/peripherals/uotghs/uotghs_otg.h ================================================================== --- at91lib/peripherals/uotghs/uotghs_otg.h +++ at91lib/peripherals/uotghs/uotghs_otg.h @@ -1,239 +0,0 @@ -/** - * \file - * - * \brief USB OTG Driver for UOTGHS. - * - * Copyright (c) 2012 - 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef UOTGHS_OTG_H_INCLUDED -#define UOTGHS_OTG_H_INCLUDED - -#include "compiler.h" - -#ifdef __cplusplus -extern "C" { -#endif - - -//! \ingroup usb_group -//! \defgroup otg_group UOTGHS OTG Driver -//! UOTGHS low-level driver for OTG features -//! -//! @{ - -/** - * \brief Initialize the dual role - * This function is implemented in uotghs_host.c file. - * - * \return \c true if the ID pin management has been started, otherwise \c false. - */ -bool otg_dual_enable(void); - -/** - * \brief Uninitialize the dual role - * This function is implemented in uotghs_host.c file. - */ -void otg_dual_disable(void); - - -//! @name UOTGHS OTG ID pin management -//! The ID pin come from the USB OTG connector (A and B receptable) and -//! allows to select the USB mode host or device. -//! The UOTGHS hardware can manage it automatically. This feature is optional. -//! When USB_ID_GPIO is defined (in board.h), this feature is enabled. -//! -//! @{ - //! Enable external OTG_ID pin (listened to by USB) -#define otg_enable_id_pin() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UIDE)) - //! Disable external OTG_ID pin (ignored by USB) -#define otg_disable_id_pin() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UIDE)) - //! Test if external OTG_ID pin enabled (listened to by USB) -#define Is_otg_id_pin_enabled() (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UIDE)) - //! Disable external OTG_ID pin and force device mode -#define otg_force_device_mode() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UIMOD), otg_disable_id_pin()) - //! Test if device mode is forced -#define Is_otg_device_mode_forced() (!Is_otg_id_pin_enabled() && Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UIMOD)) - //! Disable external OTG_ID pin and force host mode -#define otg_force_host_mode() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UIMOD), otg_disable_id_pin()) - //! Test if host mode is forced -#define Is_otg_host_mode_forced() (!Is_otg_id_pin_enabled() && !Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UIMOD)) - -//! @name UOTGHS OTG ID pin interrupt management -//! These macros manage the ID pin interrupt -//! @{ -#define otg_enable_id_interrupt() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_IDTE)) -#define otg_disable_id_interrupt() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_IDTE)) -#define Is_otg_id_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_IDTE)) -#define Is_otg_id_device() (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_ID)) -#define Is_otg_id_host() (!Is_otg_id_device()) -#define otg_ack_id_transition() (UOTGHS->UOTGHS_SCR = UOTGHS_SCR_IDTIC) -#define otg_raise_id_transition() (UOTGHS->UOTGHS_SFR = UOTGHS_SFR_IDTIS) -#define Is_otg_id_transition() (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_IDTI)) -//! @} -//! @} - -//! @name OTG Vbus management -//! @{ -#define otg_enable_vbus_interrupt() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBUSTE)) -#define otg_disable_vbus_interrupt() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBUSTE)) -#define Is_otg_vbus_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBUSTE)) -#define Is_otg_vbus_high() (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_VBUS)) -#define Is_otg_vbus_low() (!Is_otg_vbus_high()) -#define otg_ack_vbus_transition() (UOTGHS->UOTGHS_SCR = UOTGHS_SCR_VBUSTIC) -#define otg_raise_vbus_transition() (UOTGHS->UOTGHS_SFR = UOTGHS_SFR_VBUSTIS) -#define Is_otg_vbus_transition() (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_VBUSTI)) -//! @} - -//! @name UOTGHS OTG main management -//! These macros allows to enable/disable pad and UOTGHS hardware -//! @{ - //! Reset USB macro -#define otg_reset() \ - do { \ - UOTGHS->UOTGHS_CTRL = 0; \ - while( UOTGHS->UOTGHS_SR & 0x3FFF) {\ - UOTGHS->UOTGHS_SCR = 0xFFFFFFFF;\ - } \ - } while (0) - //! Enable USB macro -#define otg_enable() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_USBE)) - //! Disable USB macro -#define otg_disable() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_USBE)) -#define Is_otg_enabled() (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_USBE)) - - //! Enable OTG pad -#define otg_enable_pad() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_OTGPADE)) - //! Disable OTG pad -#define otg_disable_pad() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_OTGPADE)) -#define Is_otg_pad_enabled() (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_OTGPADE)) - - //! Check Clock Usable - //! For parts with HS feature, this one corresponding at UTMI clock -#define Is_otg_clock_usable() (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_CLKUSABLE)) - - //! Stop (freeze) internal USB clock -#define otg_freeze_clock() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_FRZCLK)) -#define otg_unfreeze_clock() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_FRZCLK)) -#define Is_otg_clock_frozen() (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_FRZCLK)) - - //! Configure time-out of specified OTG timer -#define otg_configure_timeout(timer, timeout) (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UNLOCK),\ - Wr_bitfield(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_TIMPAGE_Msk, timer),\ - Wr_bitfield(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_TIMVALUE_Msk, timeout),\ - Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UNLOCK)) - //! Get configured time-out of specified OTG timer -#define otg_get_timeout(timer) (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UNLOCK),\ - Wr_bitfield(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_TIMPAGE_Msk, timer),\ - Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UNLOCK),\ - Rd_bitfield(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_TIMVALUE_Msk)) - - - //! Get the dual-role device state of the internal USB finite state machine of the UOTGHS controller -#define otg_get_fsm_drd_state() (Rd_bitfield(UOTGHS->UOTGHS_FSM, UOTGHS_FSM_DRDSTATE_Msk)) -#define Is_otg_a_suspend() (4==otg_get_fsm_drd_state()) -#define Is_otg_a_wait_vrise() (1==otg_get_fsm_drd_state()) -//! @} - -//! @name UOTGHS OTG hardware protocol -//! These macros manages the hardware OTG protocol -//! @{ - //! Initiates a Host negotiation Protocol -#define otg_device_initiate_hnp() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_HNPREQ)) - //! Accepts a Host negotiation Protocol -#define otg_host_accept_hnp() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_HNPREQ)) - //! Rejects a Host negotiation Protocol -#define otg_host_reject_hnp() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_HNPREQ)) - //! initiates a Session Request Protocol -#define otg_device_initiate_srp() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_SRPREQ)) - //! Selects VBus as SRP method -#define otg_select_vbus_srp_method() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_SRPSEL)) -#define Is_otg_vbus_srp_method_selected() (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_SRPSEL)) - //! Selects data line as SRP method -#define otg_select_data_srp_method() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_SRPSEL)) -#define Is_otg_data_srp_method_selected() (!Is_otg_vbus_srp_method_selected()) - //! Tests if a HNP occurs -#define Is_otg_hnp() (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_HNPREQ)) - //! Tests if a SRP from device occurs -#define Is_otg_device_srp() (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_SRPREQ)) - - //! Enables HNP error interrupt -#define otg_enable_hnp_error_interrupt() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_HNPERRE)) - //! Disables HNP error interrupt -#define otg_disable_hnp_error_interrupt() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_HNPERRE)) -#define Is_otg_hnp_error_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_HNPERRE)) - //! ACKs HNP error interrupt -#define otg_ack_hnp_error_interrupt() (UOTGHS->UOTGHS_SCR = UOTGHS_SCR_HNPERRIC) - //! Raises HNP error interrupt -#define otg_raise_hnp_error_interrupt() (UOTGHS->UOTGHS_SFR = UOTGHS_SFR_HNPERRIS) - //! Tests if a HNP error occurs -#define Is_otg_hnp_error_interrupt() (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_HNPERRI)) - - //! Enables role exchange interrupt -#define otg_enable_role_exchange_interrupt() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_ROLEEXE)) - //! Disables role exchange interrupt -#define otg_disable_role_exchange_interrupt() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_ROLEEXE)) -#define Is_otg_role_exchange_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_ROLEEXE)) - //! ACKs role exchange interrupt -#define otg_ack_role_exchange_interrupt() (UOTGHS->UOTGHS_SCR = UOTGHS_SCR_ROLEEXIC) - //! Raises role exchange interrupt -#define otg_raise_role_exchange_interrupt() (UOTGHS->UOTGHS_SFR = UOTGHS_SFR_ROLEEXIS) - //! Tests if a role exchange occurs -#define Is_otg_role_exchange_interrupt() (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_ROLEEXI)) - - //! Enables SRP interrupt -#define otg_enable_srp_interrupt() (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_SRPE)) - //! Disables SRP interrupt -#define otg_disable_srp_interrupt() (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_SRPE)) -#define Is_otg_srp_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_SRPE)) - //! ACKs SRP interrupt -#define otg_ack_srp_interrupt() (UOTGHS->UOTGHS_SCR = UOTGHS_SCR_SRPIC) - //! Raises SRP interrupt -#define otg_raise_srp_interrupt() (UOTGHS->UOTGHS_SFR = UOTGHS_SFR_SRPIS) - //! Tests if a SRP occurs -#define Is_otg_srp_interrupt() (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_SRPI)) -//! @} - -//! @} - -#ifdef __cplusplus -} -#endif - - -#endif /* UOTGHS_OTG_H_INCLUDED */ ADDED atmel.mak Index: atmel.mak ================================================================== --- atmel.mak +++ atmel.mak @@ -0,0 +1,85 @@ +# Path to top level ASF directory. +ASF_PATH = /Users/dog/Applications/ARM-Toolchain/asf-3.15.0 +AT91LIB = at91lib + +# Target CPU architecture: cortex-m3, cortex-m4 +ARCH = cortex-m3 + +# Target part: none, sam3n4, etc. +PART = sam3u4e +CHIP = at91sam3u4 +BOARD = 4pi + +# Application target name. Given with suffix .a for library and .elf for a +# standalone application. +TARGET_FLASH = 4pi_flash.elf +TARGET_SRAM = 4pi_sram.elf + +include $(AT91LIB)/boards/$(BOARD)/$(CHIP)/chip.mak +include $(AT91LIB)/boards/$(BOARD)/board.mak + +CSRCS += at91lib/peripherals/adc/adc_sam3u.c +CSRCS += at91lib/peripherals/clock/sam3u/sysclk.c +CSRCS += at91lib/peripherals/delay/sam/cycle_counter.c +CSRCS += at91lib/peripherals/dmac/dmac.c +CSRCS += at91lib/peripherals/hsmci/hsmci.c +CSRCS += at91lib/peripherals/pio/pio.c +CSRCS += at91lib/peripherals/pmc/pmc.c +CSRCS += at91lib/peripherals/pmc/sleep.c +CSRCS += at91lib/peripherals/rtc/rtc.c +CSRCS += at91lib/memories/sd_mmc/sd_mmc.c +CSRCS += at91lib/memories/sd_mmc/sd_mmc_mem.c +CSRCS += at91lib/peripherals/sleepmgr/sam/sleepmgr.c +CSRCS += at91lib/peripherals/spi/spi.c +CSRCS += at91lib/peripherals/stdio/read.c +CSRCS += at91lib/peripherals/stdio/write.c +CSRCS += at91lib/peripherals/storage/ctrl_access/ctrl_access.c +CSRCS += at91lib/peripherals/twi/twi.c +CSRCS += at91lib/peripherals/uart/uart.c +CSRCS += at91lib/peripherals/usart/usart.c +CSRCS += at91lib/peripherals/usb/udc/udc.c +CSRCS += at91lib/peripherals/usb/class/cdc/device/udi_cdc_desc.c +CSRCS += at91lib/peripherals/usb/class/cdc/device/udi_cdc.c +CSRCS += at91lib/peripherals/udphs/udphs_device.c +CSRCS += at91lib/peripherals/wdt/wdt.c +CSRCS += at91lib/utility/interrupt/interrupt_sam_nvic.c +CSRCS += at91lib/utility/trace.c + +CSRCS += src/ad5206.c +CSRCS += src/charlcd.c +CSRCS += src/fattime_rtc.c +CSRCS += src/fatfs_diskio.c +CSRCS += fatfs/ff.c +CSRCS += fatfs/option/ccsbcs.c +#CSRCS += $(AT91LIB)/boards/$(BOARD)/board_lowlevel.c +#CSRCS += $(AT91LIB)/peripherals/dbgu/dbgu.c +CSRCS += src/system_sam3u.c +CSRCS += src/startup_sam3u.c +CSRCS += src/exceptions.c +#CSRCS += at91lib/peripherals/irq/nvic.c +# cmsis/sam3u/source/templates/gcc/startup_sam3u.c \ + +CSRCS += src/4pi.c + +# Path relative to top level directory pointing to a linker script. +LINKER_SCRIPT_FLASH = $(AT91LIB)/boards/$(BOARD)/$(CHIP)/flash.lds +LINKER_SCRIPT_SRAM = $(AT91LIB)/boards/$(BOARD)/$(CHIP)/sram.lds + +# Path relative to top level directory pointing to a linker script. +DEBUG_SCRIPT_FLASH = sam/boards/sam3u_ek/debug_scripts/gcc/sam3u_ek_flash.gdb +DEBUG_SCRIPT_SRAM = sam/boards/sam3u_ek/debug_scripts/gcc/sam3u_ek_sram.gdb + +CPPFLAGS += -D__SAM3U4E__ +CPPFLAGS += -DGMF_HAS_FATFS=1 + + +INCLUDES += -I$(AT91LIB)/boards/$(BOARD) +INCLUDES += -I$(AT91LIB)/peripherals +INCLUDES += -I$(AT91LIB)/components +INCLUDES += -I$(AT91LIB)/usb/device +INCLUDES += -I$(AT91LIB)/memories +INCLUDES += -I$(AT91LIB)/drivers +INCLUDES += -I$(AT91LIB)/utility +INCLUDES += -I$(AT91LIB) +INCLUDES += -Icmsis/sam3u/include +INCLUDES += -Icmsis/Include DELETED atmel.mk Index: atmel.mk ================================================================== --- atmel.mk +++ atmel.mk @@ -1,135 +0,0 @@ -# Path to top level ASF directory. -ASF_PATH = /Users/dog/Applications/ARM-Toolchain/asf-3.15.0 -AT91LIB = at91lib - -# Target CPU architecture: cortex-m3, cortex-m4 -ARCH = cortex-m3 - -# Target part: none, sam3n4, etc. -# PART = sam3u4e -# CHIP = at91sam3u4 -# BOARD = 4pi - -PART = sam3x8e -CHIP = at91sam3x8 -BOARD = due - - -# Application target name. Given with suffix .a for library and .elf for a -# standalone application. -TARGET_FLASH = due_flash.elf -TARGET_SRAM = due_sram.elf - --include $(AT91LIB)/boards/$(BOARD)/$(CHIP)/chip.mak --include $(AT91LIB)/boards/$(BOARD)/board.mak - -# CSRCS += at91lib/peripherals/adc/adc_sam3u.c -# CSRCS += at91lib/peripherals/clock/sam3u/sysclk.c -CSRCS += at91lib/peripherals/adc/adc.c -CSRCS += at91lib/peripherals/clock/sam3x/sysclk.c -CSRCS += at91lib/peripherals/delay/sam/cycle_counter.c -CSRCS += at91lib/peripherals/dmac/dmac.c -CSRCS += at91lib/peripherals/hsmci/hsmci.c -CSRCS += at91lib/peripherals/pio/pio.c -CSRCS += at91lib/peripherals/pmc/pmc.c -CSRCS += at91lib/peripherals/pmc/sleep.c -CSRCS += at91lib/peripherals/rtc/rtc.c -CSRCS += at91lib/memories/sd_mmc/sd_mmc.c -CSRCS += at91lib/memories/sd_mmc/sd_mmc_mem.c -CSRCS += at91lib/peripherals/pdc/pdc.c -CSRCS += at91lib/peripherals/pwm/pwm.c -CSRCS += at91lib/peripherals/sleepmgr/sam/sleepmgr.c -CSRCS += at91lib/peripherals/spi/spi.c -CSRCS += at91lib/peripherals/stdio/read.c -CSRCS += at91lib/peripherals/stdio/write.c -CSRCS += at91lib/peripherals/storage/ctrl_access/ctrl_access.c -CSRCS += at91lib/peripherals/twi/twi.c -CSRCS += at91lib/peripherals/uart/uart.c -CSRCS += at91lib/peripherals/usart/usart.c -CSRCS += at91lib/peripherals/usb/udc/udc.c -CSRCS += at91lib/peripherals/usb/class/cdc/device/udi_cdc_desc.c -CSRCS += at91lib/peripherals/usb/class/cdc/device/udi_cdc.c -# udphs on sam3u -# CSRCS += at91lib/peripherals/udphs/udphs_device.c -# usbotg on sam3x -CSRCS += at91lib/peripherals/uotghs/uotghs_device.c - -CSRCS += at91lib/peripherals/wdt/wdt.c -CSRCS += at91lib/utility/interrupt/interrupt_sam_nvic.c -CSRCS += at91lib/utility/trace.c - -CSRCS += src/ad5206.c -CSRCS += src/charlcd.c -CSRCS += src/fattime_rtc.c -CSRCS += src/fatfs_diskio.c -CSRCS += fatfs/ff.c -CSRCS += fatfs/option/ccsbcs.c -#CSRCS += $(AT91LIB)/boards/$(BOARD)/board_lowlevel.c -#CSRCS += $(AT91LIB)/peripherals/dbgu/dbgu.c -ifeq ($(PART), sam3u4e) - CSRCS += src/system_sam3u.c - CSRCS += src/startup_sam3u.c -endif -ifeq ($(PART), sam3x8e) - CSRCS += src/system_sam3x.c - CSRCS += src/startup_sam3x.c -endif -CSRCS += src/exceptions.c -#CSRCS += at91lib/peripherals/irq/nvic.c -# cmsis/sam3u/source/templates/gcc/startup_sam3u.c \ - -ifeq ($(BOARD), 4pi) - CSRCS += src/4pi.c -endif - -ifeq ($(BOARD), due) - CSRCS += at91lib/boards/due/init.c - CSRCS += src/due.c -endif - - -# Path relative to top level directory pointing to a linker script. -LINKER_SCRIPT_FLASH = $(AT91LIB)/boards/$(BOARD)/$(CHIP)/flash.lds -LINKER_SCRIPT_SRAM = $(AT91LIB)/boards/$(BOARD)/$(CHIP)/sram.lds - -ifneq ("$(wildcard $(LINKER_SCRIPT_FLASH))","") -else -LINKER_SCRIPT_FLASH = $(AT91LIB)/boards/$(BOARD)/$(PART)/flash.lds -endif - -# Path relative to top level directory pointing to a linker script. -ifeq ($(PART), sam3u4e) -DEBUG_SCRIPT_FLASH = sam/boards/sam3u_ek/debug_scripts/gcc/sam3u_ek_flash.gdb -DEBUG_SCRIPT_SRAM = sam/boards/sam3u_ek/debug_scripts/gcc/sam3u_ek_sram.gdb -endif - - -ifeq ($(PART), sam3u4e) -CPPFLAGS += -D__SAM3U4E__ -endif -ifeq ($(PART), sam3x8e) -CPPFLAGS += -D__SAM3X8E__ -CPPFLAGS += -DSD_MMC_ENABLE=0 -endif -CPPFLAGS += -DGMF_HAS_FATFS=1 -# CPPFLAGS += -DUDD_NO_SLEEP_MGR - -INCLUDES += -I$(AT91LIB)/boards/$(BOARD) -INCLUDES += -I$(AT91LIB)/boards/$(BOARD)/board_config -INCLUDES += -I$(AT91LIB)/boards -INCLUDES += -I$(AT91LIB)/peripherals -INCLUDES += -I$(AT91LIB)/components -INCLUDES += -I$(AT91LIB)/usb/device -INCLUDES += -I$(AT91LIB)/memories -INCLUDES += -I$(AT91LIB)/drivers -INCLUDES += -I$(AT91LIB)/utility -INCLUDES += -I$(AT91LIB) -INCLUDES += -Iatmel/hal -# INCLUDES += -Icmsis/sam3u/include -INCLUDES += -Icmsis/sam3x/include -INCLUDES += -Icmsis/Include -INCLUDES += -Iat91lib/peripherals/clock/sam3x -# INCLUDES += -I$(AT91LIB)/peripherals/usb/udc - -LIB_PATH += thirdparty/CMSIS/Lib/GCC - Index: program.cfg ================================================================== --- program.cfg +++ program.cfg @@ -26,9 +26,10 @@ halt poll #stm32f2x mass_erase 0 #flash probe 0 -flash write_image erase stm32f405h_flash.elf 0x0000000 elf +flash write_image erase build/main.elf 0x0000000 elf +# flash write_image erase build/main.bin 0x08000000 reset run shutdown Index: simulation/GiddyFirmwareSim/GiddyFirmwareSim.xcodeproj/project.pbxproj ================================================================== --- simulation/GiddyFirmwareSim/GiddyFirmwareSim.xcodeproj/project.pbxproj +++ simulation/GiddyFirmwareSim/GiddyFirmwareSim.xcodeproj/project.pbxproj @@ -57,12 +57,10 @@ DAF341851876F40E00048FAB /* SimplexNoise.m in Sources */ = {isa = PBXBuildFile; fileRef = DAF341751876F3DF00048FAB /* SimplexNoise.m */; }; DAF341861876F40E00048FAB /* VectorMath.m in Sources */ = {isa = PBXBuildFile; fileRef = DAF341781876F3DF00048FAB /* VectorMath.m */; }; DAF341881876F43A00048FAB /* OpenGL.framework in Frameworks */ = {isa = PBXBuildFile; fileRef = DAF341871876F43A00048FAB /* OpenGL.framework */; }; DAF341891876F44700048FAB /* MeshOctree.m in Sources */ = {isa = PBXBuildFile; fileRef = DAF3416D1876F3DF00048FAB /* MeshOctree.m */; }; DAF3418C1876F5D100048FAB /* Sim3DView.m in Sources */ = {isa = PBXBuildFile; fileRef = DAF3418B1876F5D100048FAB /* Sim3DView.m */; }; - DAF5703D1E61999C00306DA9 /* sp200c.c in Sources */ = {isa = PBXBuildFile; fileRef = DAF5703C1E61999C00306DA9 /* sp200c.c */; }; - DAF570521E61A3D600306DA9 /* sim.c in Sources */ = {isa = PBXBuildFile; fileRef = DAF5704C1E61A3D600306DA9 /* sim.c */; }; /* End PBXBuildFile section */ /* Begin PBXContainerItemProxy section */ DAF340DA1876ED5600048FAB /* PBXContainerItemProxy */ = { isa = PBXContainerItemProxy; @@ -193,22 +191,10 @@ DAF341791876F3DF00048FAB /* VectorMath_fixp.c */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.c; path = VectorMath_fixp.c; sourceTree = ""; }; DAF3417A1876F3DF00048FAB /* VectorMath_fixp.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = VectorMath_fixp.h; sourceTree = ""; }; DAF341871876F43A00048FAB /* OpenGL.framework */ = {isa = PBXFileReference; lastKnownFileType = wrapper.framework; name = OpenGL.framework; path = System/Library/Frameworks/OpenGL.framework; sourceTree = SDKROOT; }; DAF3418A1876F5D100048FAB /* Sim3DView.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = Sim3DView.h; sourceTree = ""; }; DAF3418B1876F5D100048FAB /* Sim3DView.m */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.objc; path = Sim3DView.m; sourceTree = ""; }; - DAF5703B1E61999C00306DA9 /* laser.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = laser.h; sourceTree = ""; }; - DAF5703C1E61999C00306DA9 /* sp200c.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; path = sp200c.c; sourceTree = ""; }; - DAF570411E61A3D600306DA9 /* board.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = board.h; sourceTree = ""; }; - DAF570431E61A3D600306DA9 /* clock.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = clock.h; sourceTree = ""; }; - DAF570451E61A3D600306DA9 /* gpio.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = gpio.h; sourceTree = ""; }; - DAF570471E61A3D600306DA9 /* pdc.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = pdc.h; sourceTree = ""; }; - DAF570491E61A3D600306DA9 /* pwm.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = pwm.h; sourceTree = ""; }; - DAF5704B1E61A3D600306DA9 /* serial.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = serial.h; sourceTree = ""; }; - DAF5704C1E61A3D600306DA9 /* sim.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; path = sim.c; sourceTree = ""; }; - DAF5704D1E61A3D600306DA9 /* sim.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = sim.h; sourceTree = ""; }; - DAF5704F1E61A3D600306DA9 /* usart.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = usart.h; sourceTree = ""; }; - DAF570511E61A3D600306DA9 /* trace.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = trace.h; sourceTree = ""; }; /* End PBXFileReference section */ /* Begin PBXFrameworksBuildPhase section */ DAF340AF1876ED5600048FAB /* Frameworks */ = { isa = PBXFrameworksBuildPhase; @@ -232,13 +218,10 @@ /* Begin PBXGroup section */ DA4A11BB18DB7E510047DC4F /* src */ = { isa = PBXGroup; children = ( - DAF570401E61A3D600306DA9 /* sim */, - DAF5703B1E61999C00306DA9 /* laser.h */, - DAF5703C1E61999C00306DA9 /* sp200c.c */, DAA442F818FCA0880044421D /* heater.c */, DAA442F918FCA0880044421D /* heater.h */, DAA442FA18FCA0880044421D /* softpwm.c */, DAA442FB18FCA0880044421D /* softpwm.h */, DA4A11BC18DB7E510047DC4F /* ad5206.c */, @@ -449,83 +432,10 @@ DAF3417A1876F3DF00048FAB /* VectorMath_fixp.h */, ); path = source; sourceTree = ""; }; - DAF570401E61A3D600306DA9 /* sim */ = { - isa = PBXGroup; - children = ( - DAF570411E61A3D600306DA9 /* board.h */, - DAF570421E61A3D600306DA9 /* clock */, - DAF570441E61A3D600306DA9 /* gpio */, - DAF570461E61A3D600306DA9 /* pdc */, - DAF570481E61A3D600306DA9 /* pwm */, - DAF5704A1E61A3D600306DA9 /* serial */, - DAF5704C1E61A3D600306DA9 /* sim.c */, - DAF5704D1E61A3D600306DA9 /* sim.h */, - DAF5704E1E61A3D600306DA9 /* usart */, - DAF570501E61A3D600306DA9 /* utility */, - ); - path = sim; - sourceTree = ""; - }; - DAF570421E61A3D600306DA9 /* clock */ = { - isa = PBXGroup; - children = ( - DAF570431E61A3D600306DA9 /* clock.h */, - ); - path = clock; - sourceTree = ""; - }; - DAF570441E61A3D600306DA9 /* gpio */ = { - isa = PBXGroup; - children = ( - DAF570451E61A3D600306DA9 /* gpio.h */, - ); - path = gpio; - sourceTree = ""; - }; - DAF570461E61A3D600306DA9 /* pdc */ = { - isa = PBXGroup; - children = ( - DAF570471E61A3D600306DA9 /* pdc.h */, - ); - path = pdc; - sourceTree = ""; - }; - DAF570481E61A3D600306DA9 /* pwm */ = { - isa = PBXGroup; - children = ( - DAF570491E61A3D600306DA9 /* pwm.h */, - ); - path = pwm; - sourceTree = ""; - }; - DAF5704A1E61A3D600306DA9 /* serial */ = { - isa = PBXGroup; - children = ( - DAF5704B1E61A3D600306DA9 /* serial.h */, - ); - path = serial; - sourceTree = ""; - }; - DAF5704E1E61A3D600306DA9 /* usart */ = { - isa = PBXGroup; - children = ( - DAF5704F1E61A3D600306DA9 /* usart.h */, - ); - path = usart; - sourceTree = ""; - }; - DAF570501E61A3D600306DA9 /* utility */ = { - isa = PBXGroup; - children = ( - DAF570511E61A3D600306DA9 /* trace.h */, - ); - path = utility; - sourceTree = ""; - }; /* End PBXGroup section */ /* Begin PBXNativeTarget section */ DAF340B11876ED5600048FAB /* GiddyFirmwareSim */ = { isa = PBXNativeTarget; @@ -641,16 +551,14 @@ DAF341851876F40E00048FAB /* SimplexNoise.m in Sources */, DAF341841876F40E00048FAB /* MersenneTwister.m in Sources */, DAF341831876F40E00048FAB /* GLString.m in Sources */, DAF3418C1876F5D100048FAB /* Sim3DView.m in Sources */, DAF340C91876ED5600048FAB /* Document.m in Sources */, - DAF5703D1E61999C00306DA9 /* sp200c.c in Sources */, DA4E9C9119EABB7200B90B92 /* HeaterSimWindowController.m in Sources */, DAF3417D1876F40E00048FAB /* gfx.m in Sources */, DA4A11B918D8EF4F0047DC4F /* VectorMath.c in Sources */, DAC022BD18DC95F6006E72E2 /* motion_control_fixp32.c in Sources */, - DAF570521E61A3D600306DA9 /* sim.c in Sources */, DAF341821876F40E00048FAB /* GLDrawableBuffer.m in Sources */, DA7963AE1ADB1CA400023489 /* MachineSim_lowlevel.c in Sources */, DAA442FC18FCA0880044421D /* heater.c in Sources */, DAF3417F1876F40E00048FAB /* GfxStateStack.m in Sources */, DAF341801876F40E00048FAB /* GfxTexture.m in Sources */, @@ -769,27 +677,19 @@ "$(inherited)", ); GCC_SYMBOLS_PRIVATE_EXTERN = NO; GCC_TREAT_INCOMPATIBLE_POINTER_TYPE_WARNINGS_AS_ERRORS = YES; GCC_WARN_64_TO_32_BIT_CONVERSION = YES; - GCC_WARN_ABOUT_MISSING_FIELD_INITIALIZERS = YES; - GCC_WARN_ABOUT_MISSING_NEWLINE = YES; GCC_WARN_ABOUT_RETURN_TYPE = YES_ERROR; - GCC_WARN_INITIALIZER_NOT_FULLY_BRACKETED = YES; GCC_WARN_UNDECLARED_SELECTOR = YES; GCC_WARN_UNINITIALIZED_AUTOS = YES; GCC_WARN_UNUSED_FUNCTION = YES; GCC_WARN_UNUSED_VARIABLE = YES; - HEADER_SEARCH_PATHS = ../../src/sim; MACOSX_DEPLOYMENT_TARGET = 10.10; ONLY_ACTIVE_ARCH = YES; SDKROOT = macosx; USER_HEADER_SEARCH_PATHS = ../../at91lib; - WARNING_CFLAGS = ( - "-Wimplicit-function-declaration", - "-Werror=implicit-function-declaration", - ); }; name = Debug; }; DAF340E51876ED5600048FAB /* Release */ = { isa = XCBuildConfiguration; @@ -812,26 +712,18 @@ ENABLE_NS_ASSERTIONS = NO; GCC_C_LANGUAGE_STANDARD = gnu99; GCC_ENABLE_OBJC_EXCEPTIONS = YES; GCC_TREAT_INCOMPATIBLE_POINTER_TYPE_WARNINGS_AS_ERRORS = YES; GCC_WARN_64_TO_32_BIT_CONVERSION = YES; - GCC_WARN_ABOUT_MISSING_FIELD_INITIALIZERS = YES; - GCC_WARN_ABOUT_MISSING_NEWLINE = YES; GCC_WARN_ABOUT_RETURN_TYPE = YES_ERROR; - GCC_WARN_INITIALIZER_NOT_FULLY_BRACKETED = YES; GCC_WARN_UNDECLARED_SELECTOR = YES; GCC_WARN_UNINITIALIZED_AUTOS = YES; GCC_WARN_UNUSED_FUNCTION = YES; GCC_WARN_UNUSED_VARIABLE = YES; - HEADER_SEARCH_PATHS = ../../src/sim; MACOSX_DEPLOYMENT_TARGET = 10.10; SDKROOT = macosx; USER_HEADER_SEARCH_PATHS = ../../at91lib; - WARNING_CFLAGS = ( - "-Wimplicit-function-declaration", - "-Werror=implicit-function-declaration", - ); }; name = Release; }; DAF340E71876ED5600048FAB /* Debug */ = { isa = XCBuildConfiguration; Index: src/charlcd.c ================================================================== --- src/charlcd.c +++ src/charlcd.c @@ -34,13 +34,10 @@ #define LCD_DAT0(x) (LCD_RS_MASK | LCD_EN_MASK | (x)) #define LCD_DAT1(x) (LCD_RS_MASK | (x)) uint32_t lcd_lastTick = 0; uint8_t lcd_backlight = 0; - -extern void clock_delay_ms(const uint32_t delay); - static void charlcd_sendRaw(uint8_t buf[], size_t buflen); static void charlcd_waitBusyLong(void) { Index: src/charlcd.h ================================================================== --- src/charlcd.h +++ src/charlcd.h @@ -12,13 +12,13 @@ #define CHARLCD_LINE0 0x00 #define CHARLCD_LINE1 0x40 #define CHARLCD_LINE2 0x14 #define CHARLCD_LINE3 0x54 -#include +#include void charlcd_init(void); void charlcd_writeString(const char* str, size_t len); void charlcd_clear(void); void charlcd_setCursor(int pos); #endif DELETED src/due.c Index: src/due.c ================================================================== --- src/due.c +++ src/due.c @@ -1,83 +0,0 @@ - -#include "gmf_config.h" -#include "machine.h" -#include "softpwm.h" - -#include -#include "gpio/gpio.h" -#include "dmac/dmac.h" -#include "sd_mmc/sd_mmc.h" -#include "usb/udc/udc.h" -#include "usb/class/cdc/device/udi_cdc.h" -#include "stdio/stdio_serial/stdio_serial.h" - -extern uint32_t SysTick_Config(uint32_t ticks); - -static void configure_console(void) -{ - const usart_serial_options_t uart_serial_options = { - .baudrate = CONF_UART_BAUDRATE, - .paritytype = US_MR_PAR_NO - }; - - /* Configure console UART. */ - sysclk_enable_peripheral_clock(CONSOLE_UART_ID); - stdio_serial_init(CONSOLE_UART, &uart_serial_options); - - uart_enable_rx(CONSOLE_UART); - uart_enable_tx(CONSOLE_UART); -} - -static void steppers_init(void) -{ - // default to HIGH output for /EN, so that drivers remain inactive - gpio_configure_group(PIOA, STEPPERS_A_PINMASK, PIO_TYPE_PIO_OUTPUT_1); - gpio_configure_group(PIOB, STEPPERS_B_PINMASK, PIO_TYPE_PIO_OUTPUT_1); - gpio_configure_group(PIOC, STEPPERS_C_PINMASK, PIO_TYPE_PIO_OUTPUT_1); - - int32_t uSteps[] = MACHINE_MICROSTEPS; - - #if defined(STEPX_MS1_GPIO) && defined(STEPX_MS2_GPIO) - stepper_config_ustep(STEPX_MS1_GPIO, STEPX_MS2_GPIO, uSteps[0]); - #endif - #if defined(STEPY_MS1_GPIO) && defined(STEPY_MS2_GPIO) - stepper_config_ustep(STEPY_MS1_GPIO, STEPY_MS2_GPIO, uSteps[1]); - #endif - #if defined(STEPZ_MS1_GPIO) && defined(STEPZ_MS2_GPIO) - stepper_config_ustep(STEPZ_MS1_GPIO, STEPZ_MS2_GPIO, uSteps[2]); - #endif - #if defined(STEPA_MS1_GPIO) && defined(STEPA_MS2_GPIO) - stepper_config_ustep(STEPA_MS1_GPIO, STEPA_MS2_GPIO, uSteps[3]); - #endif - #if defined(STEPB_MS1_GPIO) && defined(STEPB_MS2_GPIO) - stepper_config_ustep(STEPB_MS1_GPIO, STEPB_MS2_GPIO, uSteps[4]); - #endif -} - - -void init_due(void) -{ - /* Initialize the SAM system */ - sysclk_init(); - SysTick_Config(sysclk_get_cpu_hz()/STEPPER_TICK_HZ); - ioport_init(); - dmac_init(DMAC); - board_init(); - spwm_init(); - - configure_console(); - - sd_mmc_init(); - steppers_init(); - - // // init digital potentiometers for current setting - // ad5206_init(SPI); - // - // int currents[MACHINE_NUM_AXES] = MACHINE_CURRENT_CTRL; - // - // for (int i = 0; i < MACHINE_NUM_AXES; ++i) - // ad5206_setValue(i, currents[i]); - - -} - DELETED src/due.h Index: src/due.h ================================================================== --- src/due.h +++ src/due.h @@ -1,101 +0,0 @@ -#ifndef DUE_H -#define DUE_H - -#include "board.h" - -void init_due(void); - - -#define STEPPERS_A_PINMASK (0) -#define STEPPERS_B_PINMASK (0) -#define STEPPERS_C_PINMASK (PIO_PC1 | PIO_PC3 | PIO_PC5 | PIO_PC7 | PIO_PC9 | PIO_PC12 | PIO_PC14 | PIO_PC16 | PIO_PC18) - - -// #define STEPDBG_DIR_GPIO PIO_PB20_IDX -// #define STEPDBG_STEP_GPIO PIO_PB21_IDX -// #define STEPDBG_TICK_GPIO PIO_PB19_IDX -// #define STEPDBG_TIM0_GPIO PIO_PB22_IDX -// #define STEPDBG_TIM1_GPIO PIO_PB23_IDX -// #define STEPDBG_TIM2_GPIO PIO_PB24_IDX -// #define STEPDBG_TIM3_GPIO PIO_PB25_IDX - -#define STEPX_EN_GPIO PIO_PC16_IDX -#define STEPX_DIR_GPIO PIO_PC14_IDX -#define STEPX_STEP_GPIO PIO_PC12_IDX -// #define STEPX_MS1_GPIO PIO_PC30_IDX -// #define STEPX_MS2_GPIO PIO_PC29_IDX - -#define STEPY_EN_GPIO PIO_PC7_IDX -#define STEPY_DIR_GPIO PIO_PC9_IDX -#define STEPY_STEP_GPIO PIO_PC18_IDX -// #define STEPY_MS1_GPIO PIO_PC11_IDX -// #define STEPY_MS2_GPIO PIO_PC10_IDX - -#define STEPZ_EN_GPIO PIO_PC1_IDX -#define STEPZ_DIR_GPIO PIO_PC3_IDX -#define STEPZ_STEP_GPIO PIO_PC5_IDX -// #define STEPZ_MS1_GPIO PIO_PB6_IDX -// #define STEPZ_MS2_GPIO PIO_PB5_IDX - -// #define STEPA_EN_GPIO PIO_PB13_IDX -// #define STEPA_DIR_GPIO PIO_PB2_IDX -// #define STEPA_STEP_GPIO PIO_PC26_IDX -// #define STEPA_MS1_GPIO PIO_PB12_IDX -// #define STEPA_MS2_GPIO PIO_PB11_IDX -// -// #define STEPB_EN_GPIO PIO_PC13_IDX -// #define STEPB_DIR_GPIO PIO_PC25_IDX -// #define STEPB_STEP_GPIO PIO_PB1_IDX -// #define STEPB_MS1_GPIO PIO_PB0_IDX -// #define STEPB_MS2_GPIO PIO_PC24_IDX - -#define ENDSTOP_XMIN_GPIO PIO_PD2_IDX -#define ENDSTOP_XMAX_GPIO PIO_PD6_IDX -#define ENDSTOP_YMIN_GPIO PIO_PD9_IDX -#define ENDSTOP_YMAX_GPIO PIO_PD10_IDX -#define ENDSTOP_ZMIN_GPIO PIO_PD5_IDX -#define ENDSTOP_ZMAX_GPIO PIO_PD4_IDX - -#define ENDSTOP_FLAGS (PIO_TYPE_PIO_INPUT | PIO_PULLUP | PIO_DEBOUNCE) - -#define PIN_LASER_PSU_IDX PIO_PC17_IDX -#define PIN_LASER_INTERLOCK_IDX PIO_PC8_IDX - -// PWMH1 -#define PIN_LASER_PWM_IDX PIO_PA19_IDX -#define PWM_CHANNEL_LASER PWM_CHANNEL_1 - -#define PIN_LASER_LOCK_SENSE_IDX PIO_PA14_IDX -#define PIN_LASER_ALRM_SENSE_IDX PIO_PA15_IDX -#define PIN_LASER_EMBUT_SENSE_IDX PIO_PA7_IDX - -#define PIN_LASER_PWR_MON_IDX PIO_PB20_IDX -#define PIN_LASER_DIODE_MON_IDX PIO_PB19_IDX -#define PIN_LASER_ANALOG_POWER_IDX PIO_PB16_IDX - -#define LASER_PWM_FLAGS (PIO_TYPE_PIO_PERIPH_B) - -#define LASER_LOCK_SENSE_FLAGS (PIO_TYPE_PIO_INPUT | PIO_PULLUP) -#define LASER_ALRM_SENSE_FLAGS (PIO_TYPE_PIO_INPUT | PIO_PULLUP) -#define LASER_EMBUT_SENSE_FLAGS (PIO_TYPE_PIO_INPUT | PIO_PULLUP) -// these ADC inputs bypass GPIO config -#define LASER_PWR_MON_FLAGS (PIO_DEFAULT) -#define LASER_DIODE_MON_FLAGS (PIO_DEFAULT) -// DAC also special function -#define LASER_ANALOG_POWER_FLAGS (PIO_DEFAULT) - -#define ID_LASER_USART ID_USART0 -#define LASER_USART USART0 -#define PIN_LASER_RXD_IDX PIN_USART0_RXD_IDX -#define PIN_LASER_TXD_IDX PIN_USART0_TXD_IDX -#define PIN_LASER_RXD_FLAGS PIN_USART0_RXD_FLAGS -#define PIN_LASER_TXD_FLAGS PIN_USART0_TXD_FLAGS - -// #define ID_LASER_USART ID_USART1 -// #define LASER_USART USART1 -// #define PIN_LASER_RXD_IDX PIN_USART1_RXD_IDX -// #define PIN_LASER_TXD_IDX PIN_USART1_TXD_IDX -// #define PIN_LASER_RXD_FLAGS PIN_USART1_RXD_FLAGS -// #define PIN_LASER_TXD_FLAGS PIN_USART1_TXD_FLAGS - -#endif // DUE_H Index: src/exceptions.c ================================================================== --- src/exceptions.c +++ src/exceptions.c @@ -88,13 +88,10 @@ void PIOA_Handler(void) __attribute__ ((weak, alias("Dummy_Handler"))); void PIOB_Handler(void) __attribute__ ((weak, alias("Dummy_Handler"))); #ifdef ID_PIOC void PIOC_Handler(void) __attribute__ ((weak, alias("Dummy_Handler"))); #endif -#ifdef ID_PIOD -void PIOD_Handler(void) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif void USART0_Handler(void) __attribute__ ((weak, alias("Dummy_Handler"))); void USART1_Handler(void) __attribute__ ((weak, alias("Dummy_Handler"))); void USART2_Handler(void) __attribute__ ((weak, alias("Dummy_Handler"))); #ifdef ID_USART3 void USART3_Handler(void) __attribute__ ((weak, alias("Dummy_Handler"))); @@ -101,43 +98,18 @@ #endif void HSMCI_Handler(void) __attribute__ ((weak, alias("Dummy_Handler"))); void TWI0_Handler(void) __attribute__ ((weak, alias("Dummy_Handler"))); void TWI1_Handler(void) __attribute__ ((weak, alias("Dummy_Handler"))); void SPI_Handler(void) __attribute__ ((weak, alias("Dummy_Handler"))); -#ifdef ID_SPI0 -void SPI0_Handler(void) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif void SSC_Handler(void) __attribute__ ((weak, alias("Dummy_Handler"))); void TC0_Handler(void) __attribute__ ((weak, alias("Dummy_Handler"))); void TC1_Handler(void) __attribute__ ((weak, alias("Dummy_Handler"))); void TC2_Handler(void) __attribute__ ((weak, alias("Dummy_Handler"))); -#ifdef ID_TC3 -void TC3_Handler(void) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_TC4 -void TC4_Handler(void) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_TC5 -void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif -#ifdef _SAM3XA_TC2_INSTANCE_ -void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif /* _SAM3XA_TC2_INSTANCE_ */ -void PWM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void ADC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void UOTGHS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#ifdef _SAM3XA_EMAC_INSTANCE_ -void EMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif /* _SAM3XA_EMAC_INSTANCE_ */ -void CAN0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void CAN1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PWM_Handler(void) __attribute__ ((weak, alias("Dummy_Handler"))); void ADC12B_Handler(void) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC_Handler(void) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_Handler(void) __attribute__ ((weak, alias("Dummy_Handler"))); void UDPHS_Handler(void) __attribute__ ((weak, alias("Dummy_Handler"))); #endif /* __GNUC__ */ #ifdef __ICCARM__ /* Cortex-M3 core handlers */ Index: src/exceptions.h ================================================================== --- src/exceptions.h +++ src/exceptions.h @@ -42,15 +42,11 @@ */ #ifndef EXCEPTIONS_H_INCLUDED #define EXCEPTIONS_H_INCLUDED -#if defined(__SAM3U4E__) #include "sam3u.h" -#elif defined(__SAM3X8E__) -#include "sam3xa.h" -#endif /* @cond 0 */ /**INDENT-OFF**/ #ifdef __cplusplus extern "C" { Index: src/gcode_interpreter.c ================================================================== --- src/gcode_interpreter.c +++ src/gcode_interpreter.c @@ -4,20 +4,18 @@ // // Created by Dömötör Gulyás on 04.10.2013. // Copyright (c) 2013 Dömötör Gulyás. All rights reserved. // - -#include "board.h" #include "machine.h" +#include "board.h" #include "gcode_interpreter.h" #include "fixp32.h" #include "motion_control_fixp32.h" #include "motion_planner_fixp32.h" #include "heater.h" #include "softpwm.h" -#include "laser.h" #include #include #include @@ -42,20 +40,10 @@ #include #include "fatfs/ff.h" #elif defined(boardstm32f405h) #include "usbd_cdc_if.h" -#elif defined(due) -#include -#include - -#include "usb/udc/udc.h" -#include "usb/class/cdc/device/udi_cdc.h" - -#include -#include "fatfs/ff.h" - #endif #endif //#define ENABLE_MOTION_TRACING 1 @@ -79,84 +67,10 @@ return &shared_self; } #endif -/* - used/known Gcodes: - A,B,C secondary axes - D NA - E extrusion feed - F feedrate - G G codes - G0 rapid motion - G1 coordinated motion - G2 CW arc - G3 CCW arc - G4 dwell - (S.. seconds) - P.. milliseconds - G21 set units to mm - G28 home all or given axis - G80 cancel modal motion - G90 use absolute positioning - G91 use relative positioning - G92 set current position - - H heater calibration - I,J,K additional parameters - L NA - M M codes - M0 halt - M1 pause - M3 spindle on - M4 spindle on reverse - M5 spindle off - M7 coolant A on - M8 cooland B on - M9 coolant off - M10 aux0 on (vacuum/clamp) - M11 aux1 off - M17 steppers enable - M18 steppers disable - M21-M30 reprap SD card handling - M80 power on - M81 power off - M106 fan on - M107 fan off - M112 emergency stop - M115 get firmware version - M140 set bed temp - M245 start cooler - M246 stop cooler - M294 targeting laser on - M295 targeting laser off - M296 Laser interlock on - M297 Laser interlock off - M298 Laser PSU on - M299 Laser PSU off - M999 restart after error - - N line number - O - P pause - Q - R - S spindle speed / fan duty cycle - T tool change - U,V,W additional params - X,Y,Z primary axes - - */ - - #define MCODE_294_TARGETING_LASER_ON 294 - #define MCODE_295_TARGETING_LASER_OFF 295 - #define MCODE_296_LASER_INTERLOCK_ON 296 - #define MCODE_297_LASER_INTERLOCK_OFF 297 - #define MCODE_298_LASER_PSU_ON 298 - #define MCODE_299_LASER_PSU_OFF 299 - #define kRS274DistanceModeBit 0 #define kRS274DistanceModeAbsolute 0 #define kRS274DistanceModeRelative 1 #define kRS274MotionModeBit 1 @@ -277,11 +191,11 @@ static void sendGCodeString(const char* s, size_t length) { #ifndef MACHINE_SIMULATION -#if defined(board4pi) || defined(due) +#if defined(board4pi) iram_size_t bytesRemain = length; while ((bytesRemain = udi_cdc_multi_write_buf(UDI_CDC_DATA_EP_IN_0, s, bytesRemain))); #endif #if defined(boardstm32f405h) size_t bytesRemain = length; @@ -451,24 +365,19 @@ { case 'G': switch (iv) { case 92: - SETBIT(self->rs274ModalMode, kRS274AxisOffsetBit, kRS274AxisOffsetExpected); + SETBIT(self->rs247ModalMode, kRS274AxisOffsetBit, kRS274AxisOffsetExpected); break; } break; } } } -/** - G90 - G91 -*/ - static void _interpretDistanceModeCommands(gcode_interpreter_t* self, GCodeParser* parser) { for (int i = 0; i < parser->numCommandsReceived; ++i) { //int64_t dd = parser->lineCommandValues[i].decimalFactor; @@ -477,26 +386,23 @@ { case 'G': switch (iv) { case 90: - SETBIT(self->rs274ModalMode, kRS274DistanceModeBit, kRS274DistanceModeAbsolute); + SETBIT(self->rs247ModalMode, kRS274DistanceModeBit, kRS274DistanceModeAbsolute); break; case 91: - SETBIT(self->rs274ModalMode, kRS274DistanceModeBit, kRS274DistanceModeRelative); + SETBIT(self->rs247ModalMode, kRS274DistanceModeBit, kRS274DistanceModeRelative); break; } break; } } } -/** - G0 - G1 -*/ + static void _interpretModalMotionCommands(gcode_interpreter_t* self, GCodeParser* parser) { for (int i = 0; i < parser->numCommandsReceived; ++i) { //int64_t dd = parser->lineCommandValues[i].decimalFactor; @@ -506,26 +412,23 @@ case 'G': { switch (iv) { case 0: - SETBIT(self->rs274ModalMode, kRS274MotionModeBit, kRS274MotionModeRapid); + SETBIT(self->rs247ModalMode, kRS274MotionModeBit, kRS274MotionModeRapid); break; case 1: - SETBIT(self->rs274ModalMode, kRS274MotionModeBit, kRS274MotionModeFeed); + SETBIT(self->rs247ModalMode, kRS274MotionModeBit, kRS274MotionModeFeed); break; } break; } } } } -/** - Fxxx -*/ static void _interpretFeedRateCommands(gcode_interpreter_t* self, GCodeParser* parser) { for (int i = 0; i < parser->numCommandsReceived; ++i) { @@ -540,14 +443,10 @@ } } - -/** - G28 home axes -*/ static void _interpretHomingCommands(gcode_interpreter_t* self, GCodeParser* parser) { int homingCommmandDetected = 0; int homeX = 0; int homeY = 0; @@ -581,21 +480,20 @@ } } } - // if no homing axis was specified, home all axes if (!homeX && !homeY && !homeZ) homeX = homeY = homeZ = 1; if (homingCommmandDetected) { _performHoming(self, homeX, homeY, homeZ); } } -#if !defined(MACHINE_SIMULATION) && defined(GMF_HAS_FATFS) +#if !defined(MACHINE_SIMULATION) && defined(board4pi) /** Size of the file to write/read. */ #define DATA_SIZE 2048 /** Test settings: Number of bytes to test */ #define TEST_SIZE (4 * 1024) @@ -811,16 +709,10 @@ return 1; } #endif -/** - H heater calibration - M17 - M18 - M20 SD card test -*/ static int _interpretAuxiliaryCommands(gcode_interpreter_t* self, GCodeParser* parser) { int turnFanOn = 0; int turnFanOff = 0; int setExtruderTemp = 0; @@ -994,40 +886,10 @@ { setBedTemp = 1; waitBedTemp = 1; break; } - case MCODE_294_TARGETING_LASER_ON: - { - laser_enableTargetingLaser(true); - break; - } - case MCODE_295_TARGETING_LASER_OFF: - { - laser_enableTargetingLaser(false); - break; - } - case MCODE_296_LASER_INTERLOCK_ON: - { - laser_enableInterlock(true); - break; - } - case MCODE_297_LASER_INTERLOCK_OFF: - { - laser_enableInterlock(false); - break; - } - case MCODE_298_LASER_PSU_ON: - { - laser_enablePowerSupply(true); - break; - } - case MCODE_299_LASER_PSU_OFF: - { - laser_enablePowerSupply(false); - break; - } } break; } case 'S': { @@ -1505,11 +1367,11 @@ } if (foundMotion) { - if (GETBIT(self->rs274ModalMode, kRS274DistanceModeBit) == kRS274DistanceModeAbsolute) + if (GETBIT(self->rs247ModalMode, kRS274DistanceModeBit) == kRS274DistanceModeAbsolute) { for (int i = 0; i < MP_NUM_AXES; ++i) { if (foundAxes[i] != 0) { @@ -1527,11 +1389,11 @@ } } } // axis offset without moving - if (GETBIT(self->rs274ModalMode, kRS274AxisOffsetBit) == kRS274AxisOffsetExpected) + if (GETBIT(self->rs247ModalMode, kRS274AxisOffsetBit) == kRS274AxisOffsetExpected) { for (int i = 0; i < MP_NUM_AXES; ++i) { if (foundAxes[i] != 0) @@ -1539,11 +1401,11 @@ int32_t targetSteps = _decimalCoordToSteps(self->gcodeTargetPositions[i], i); self->gcodeSubmittedSteps[i] = targetSteps; } } - SETBIT(self->rs274ModalMode, kRS274AxisOffsetBit, kRS274AxisOffsetKeep); + SETBIT(self->rs247ModalMode, kRS274AxisOffsetBit, kRS274AxisOffsetKeep); } else // actually move { self->motionHandler(self, self->motionHandlerContext); } @@ -1563,18 +1425,16 @@ _interpretMotionTargetCommands(self, parser); } static void _sendGCodeResponse(const char* buf, const size_t len) { -#if defined(board4pi) || defined(due) +#if defined(board4pi) size_t bytesRemain = len; while ((bytesRemain = udi_cdc_multi_write_buf(UDI_CDC_DATA_EP_IN_0, buf, bytesRemain))); #elif defined(boardstm32f405h) int err = USBD_BUSY; while ((err = CDC_Transmit_FS(buf, len)) != USBD_OK) {}; -#elif defined(MACHINE_SIMULATION) - printf("REPL: %.*s", (int)len, buf); #else #error gcode response undefined for build target #endif } @@ -1584,10 +1444,32 @@ // TRACE_INFO("EOL!\r\n"); TRACE_INFO("!"); int responseSent = 0; + /* + used Gcodes: + A,B,C secondary axes + D NA + E extrusion feed + F feedrate + G G codes + H heater calibration + I,J,K additional parameters + L NA + M M codes + N line number + O + P pause + Q + R + S fan duty cycle + T tool change + U,V,W additional params + X,Y,Z primary axes + + */ // update target positions (for relative moves) memcpy(self->gcodeTargetPositions, self->gcodeSubmittedPositions, sizeof (self->gcodeTargetPositions)); @@ -1624,11 +1506,11 @@ _interpretMotionCommands(self, s); responseSent = responseSent || _interpretAuxiliaryCommands(self, s); //commands = [self interpretStopCommands: commands]; // reset non-modal gcodes - SETBIT(self->rs274ModalMode, kRS274AxisOffsetBit, kRS274AxisOffsetKeep); + SETBIT(self->rs247ModalMode, kRS274AxisOffsetBit, kRS274AxisOffsetKeep); #ifndef MACHINE_SIMULATION if (!responseSent) { @@ -1652,11 +1534,11 @@ } self->gcodeTargetFeedRate = (Decimal){6000,1,1}; self->gcodeSelectedTool = (Decimal){0,1,1}; - self->rs274ModalMode = 0; + self->rs247ModalMode = 0; self->opState = GCI_NORMAL; self->motionHandler = _defaultMotionHandler; } Index: src/gcode_interpreter.h ================================================================== --- src/gcode_interpreter.h +++ src/gcode_interpreter.h @@ -46,11 +46,11 @@ Decimal gcodeSelectedTool; size_t commandCounter; int gcodeExtruderPositionRelative; - uint32_t rs274ModalMode; + uint32_t rs247ModalMode; GCodeInterpreterState opState; struct mctrl_state_s* mctrl; struct mplan_state_s* planner; Index: src/gcode_parser.c ================================================================== --- src/gcode_parser.c +++ src/gcode_parser.c @@ -63,22 +63,19 @@ gcode_newline_reset(s); } - - int gcode_consume_char(GCodeParser* s, int8_t c, int port) { - // TRACE_INFO("gcode_consume_char(%d, '%c')\r\n", s->state, c); - + switch (s->state) { case kGCodeStateLineEnd: { - // TRACE_INFO("calling eolHandler()\r\n"); + if (s->eolHandler) s->eolHandler(s, s->eolHandlerContext); s->state = kGCodeStateNewLine; return 0; @@ -135,27 +132,26 @@ { s->checksum = s->checksum ^ c; switch (c) { - case '\r': + case '\n': { - // TRACE_INFO("newline!\r\n"); s->state = kGCodeStateLineEnd; return 0; break; } case ' ': case '\t': - case '\n': + case '\r': { // ignore break; } case '*': { - s->checksum = s->checksum ^ c; // xor again to remove star + s->checksum = s->checksum ^ c; // xor again to remove s->receivedChecksum = 0; s->state = kGCodeStateChecksum; break; } case ';': @@ -268,13 +264,12 @@ s->commandLetter = 0; s->state = kGCodeStateDefault; s->numCommandsReceived++; return 0; } - // case kGCodeStateComment: } return 1; } DELETED src/gmf_config.h Index: src/gmf_config.h ================================================================== --- src/gmf_config.h +++ src/gmf_config.h @@ -1,13 +0,0 @@ -#ifndef GMF_CONGIF_H -#define GMF_CONGIF_H - -#include "board.h" - -#if defined(due) -#include "due.h" -#elif defined(board4pi) -#include "4pi.h" -#endif - - -#endif // GMF_CONGIF_H Index: src/heater.c ================================================================== --- src/heater.c +++ src/heater.c @@ -483,11 +483,11 @@ //heaters[self->channel].model.currentTempKelvin = temp; TRACE_WARNING("H%d: calibrated to Td=%.1f, C=%.1f J/K, Pa=%.1f mW, DE=%.1f Ks\r\n", self->channel, heaters[self->channel].heatDelay, heaters[self->channel].heatCapacity, heaters[self->channel].baseFlux, heaters[self->channel].heatErrorAccumulatorThreshold); spwm_setThreshold(self->channel, 0x3FF, 0); // disable power -#if defined (board4pi) +#ifndef MACHINE_SIMULATION #define copynext(dst,src,size) (size+(uint8_t*)memcpy(dst,src,size)) size_t bufsize = _CALIB_TOTAL_NUMFLOATS*sizeof(float) + sizeof(self->measurements); uint8_t buf[bufsize]; DELETED src/laser.h Index: src/laser.h ================================================================== --- src/laser.h +++ src/laser.h @@ -1,35 +0,0 @@ -#ifndef LASER_H -#define LASER_H - -#include "fixp32.h" -#include -#include - - - -/// init RS232 comms etc -void laser_init(void); - -/// call from idle loop for idle processing of eg. serial comms -void laser_idle(void); - -/// RL=X -void laser_enableTargetingLaser(bool const en); -void laser_setBeamPowerAnalog_W(fix16d16_t const power); - -/// P=xxx.x -void laser_setBeamPowerDigital_W(fix16d16_t const power); -void laser_setBeamPowerPwm(fix16d16_t const pwm); - -/// A? -void laser_asyncGetAlarmsRaw(char* const buf, size_t const buflen); -/// K? -void laser_asyncGetInterlockStatusRaw(char* const buf, size_t const buflen); - -/// open solenoid valve on cooling circuit (UU) -void laser_openCoolingValve(void); - -void laser_enableInterlock(bool const en); -void laser_enablePowerSupply(bool const en); - -#endif // LASER_H Index: src/machine.c ================================================================== --- src/machine.c +++ src/machine.c @@ -13,45 +13,29 @@ #include "board.h" #include "machine.h" #include "motion_control_fixp32.h" #include "softpwm.h" -#if defined(due) -#include "due.h" -#endif - #include void machine_psOn(void) { TRACE_INFO("Turning ON Power Supply.\r\n"); - #ifdef MACHINE_PIN_PSON_GPIO MACHINE_PIN_PSON_LEVEL ? GPIO_PIN_SET(MACHINE_PIN_PSON_GPIO) : GPIO_PIN_CLR(MACHINE_PIN_PSON_GPIO); - #endif - #ifdef MACHINE_PIN_PSON_MOTORS_GPIO - MACHINE_PIN_PSON_LEVEL ? GPIO_PIN_SET(MACHINE_PIN_PSON_MOTORS_GPIO) : GPIO_PIN_CLR(MACHINE_PIN_PSON_MOTORS_GPIO); - #endif + } void machine_psOff(void) { TRACE_INFO("Turning OFF Power Supply.\r\n"); - #ifdef MACHINE_PIN_PSON_GPIO MACHINE_PIN_PSON_LEVEL ? GPIO_PIN_CLR(MACHINE_PIN_PSON_GPIO) : GPIO_PIN_SET(MACHINE_PIN_PSON_GPIO); - #endif - #ifdef MACHINE_PIN_PSON_MOTORS_GPIO - MACHINE_PIN_PSON_LEVEL ? GPIO_PIN_CLR(MACHINE_PIN_PSON_MOTORS_GPIO) : GPIO_PIN_SET(MACHINE_PIN_PSON_MOTORS_GPIO); - #endif } void machine_enableSteppers(void) { - // power supply enable - - // logical enable GPIO_PIN_CLR(STEPX_EN_GPIO); GPIO_PIN_CLR(STEPY_EN_GPIO); GPIO_PIN_CLR(STEPZ_EN_GPIO); #if MC_NUM_AXES >= 4 GPIO_PIN_CLR(STEPA_EN_GPIO); Index: src/machine.h ================================================================== --- src/machine.h +++ src/machine.h @@ -49,12 +49,11 @@ #define MACHINE_AXIS_HOMING_SPEED_MM_PER_MIN {MC_DEF2(600,1, 600,1, 300,1, 0,0, 0,0, 0,0)} #define MACHINE_AXIS_HOMING_TOLERANCE_MM {MC_DEF3(1,10,-1, 1,10,-1, 1,10,-1, 0,0,0, 0,0,0, 0,0,0)} #define MACHINE_AXIS_HOMING_ORDER {MC_DEF(0,1,2,-1,-1,-1)} #define MACHINE_AXIS_HOMING_LEVEL {MC_DEF(1,1,1,-1,-1,-1)} -// #define MACHINE_NUM_HEATERS (3) -#define MACHINE_NUM_HEATERS (0) +#define MACHINE_NUM_HEATERS (3) #define MACHINE_HEATER0_SPWM_CHANNEL (0) #define MACHINE_HEATER1_SPWM_CHANNEL (1) #define MACHINE_HEATER2_SPWM_CHANNEL (2) #define MACHINE_AUX0_SPWM_CHANNEL (3) @@ -92,23 +91,13 @@ #define MACHINE_FILAMENT_TYPE {FILAMENT_TYPE_PLA,FILAMENT_TYPE_PLA} #if defined(board4pi) #define MACHINE_PIN_PSON_GPIO (PIO_PB31_IDX) #define MACHINE_PIN_PSON_FLAGS (PIO_OUTPUT_0) -#elif defined(due) - #define MACHINE_PIN_PSON_GPIO (PIO_PC15_IDX) - #define MACHINE_PIN_PSON_FLAGS (PIO_OUTPUT_0) - - #define MACHINE_PIN_PSON_LASER_GPIO (PIO_PC17_IDX) - #define MACHINE_PIN_PSON_LASER_FLAGS (PIO_OUTPUT_0) - - #define MACHINE_PIN_PSON_MOTORS_GPIO (PIO_PC13_IDX) - #define MACHINE_PIN_PSON_MOTORS_FLAGS (PIO_OUTPUT_0) #elif defined(boardstm32f405h) #define MACHINE_PIN_PSON_GPIO GPIO_MAP(MOTOR_PSU) #endif - #define MACHINE_PIN_PSON_LEVEL (1) extern void machine_psOn(void); extern void machine_psOff(void); extern void machine_enableSteppers(void); @@ -128,12 +117,11 @@ { return MSIM_CPU_HZ/MSIM_TICK_HZ; } #else -#if defined(board4pi) || defined(due) - +#if defined(board4pi) #define GPIO_PIN_SET(pin) \ (((Pio *)((uint32_t)PIOA + (PIO_DELTA * (pin >> 5))))->PIO_SODR = 1 << (pin & 0x1F)) #define GPIO_PIN_CLR(pin) \ (((Pio *)((uint32_t)PIOA + (PIO_DELTA * (pin >> 5))))->PIO_CODR = 1 << (pin & 0x1F)) Index: src/main.c ================================================================== --- src/main.c +++ src/main.c @@ -44,11 +44,11 @@ #include #include "charlcd.h" #include "gcode_parser.h" #include "gcode_interpreter.h" -#if defined(at91sam3u4) || defined(at91sam3x8) +#if defined(at91sam3u4) #include "ad5206.h" #include #include "uart/uart.h" #include "dmac/dmac.h" #include "adc/adc.h" @@ -63,29 +63,22 @@ #include "errno.h" #include "usbd_def.h" #include "usbd_cdc_if.h" #include "clock/clock.h" -#include - #endif #include #include "machine.h" #include "heater.h" -#include "laser.h" #include "softpwm.h" #include "motion_control_fixp32.h" #include "gpio/gpio.h" #include "pio/pio.h" #include #include -#include #include "fatfs/ff.h" - -#include "gmf_config.h" - #include #include #include #include @@ -148,24 +141,20 @@ #define clock_get_main_freq() sysclk_get_main_hz() #define clock_get_cpu_freq() sysclk_get_cpu_hz() #define clock_get_peripheral_freq() sysclk_get_peripheral_hz() #endif -#define GPIO_PIN_TOGGLE(pin) gpio_toggle_pin(pin) - - -#if defined(board4pi) || defined(due) -void read_usbser_atmel(void) +#if defined(board4pi) +void read_usbser_4pi(void) { uint8_t port = 0; size_t bytesRemaining = udi_cdc_multi_get_nb_received_data(port); if (bytesRemaining) { int c = udi_cdc_multi_getc(port); int nc = 0; - TRACE_INFO("reading %ld data '%c'\r\n", bytesRemaining, c); while (!(nc = gcode_consume_char(&gcodeParser, c, port))) {}; } } @@ -241,25 +230,20 @@ } #endif } extern int stm32_main(void); -extern int stm32_init(void); - int main(void) { // Pin LEDPINS[]={PINS_LEDS}; // return stm32_main(); -#if defined(due) - init_due(); -#elif defined(board4pi) +#if defined(board4pi) init_4pi(); #elif defined(boardstm32f405h) - stm32_init(); - // usb_cdc_init(); + init_stm32f405h(); #endif mctrl_init(mctrl_sharedState(), NULL); puts(STRING_HEADER); @@ -275,12 +259,10 @@ charlcd_setCursor(CHARLCD_LINE3); charlcd_writeString("Hello!", 6); #endif heater_init(gHeaters, MACHINE_NUM_HEATERS); - - laser_init(); sg_planner_init(sg_sharedState()); gint_init(gint_sharedState()); gcode_init(&gcodeParser); mplan_init(&planner); @@ -289,11 +271,11 @@ gint_sharedState()->heaters = gHeaters; gcodeParser.eolHandler = gcode_eol_handler; // start Atmel USB Device Controller -#if defined(board4pi) || defined(due) +#if defined(board4pi) udc_start(); #endif int toggle = 0; @@ -322,17 +304,16 @@ uint32_t lastHalfSecondTick = clock_uptime_ms(); while (1) { - // CDC_Transmit_FS("Hello\n", 6); const uint32_t tickCount = clock_uptime_ms(); _attemptSdCardMount(tickCount); -#if defined(board4pi) || defined(due) - read_usbser_atmel(); +#if defined(board4pi) + read_usbser_4pi(); #elif defined(boardstm32f405h) // usb input processed in callback, not in main loop #endif // uint8_t port = 0; // size_t bytesRemaining = udi_cdc_multi_get_nb_received_data(port); @@ -344,14 +325,11 @@ // // while (!(nc = gcode_consume_char(&gcodeParser, c, port))) // {}; // } - laser_idle(); - - // alive tick if (tickCount - lastHalfSecondTick > 500) { static const char progressString[4] = {'-','\\','|','/'}; static size_t progressIndex; lastHalfSecondTick += 500; @@ -392,14 +370,14 @@ void USART6_IRQHandler(void) { } -// void USART3_IRQHandler(void) -// { -// -// } +void USART3_IRQHandler(void) +{ + +} void mplan_ext_triggerPlanner(void* context) { TRACE_ERROR("mplan_ext_triggerPlanner() not implemented.\r\n"); @@ -426,53 +404,41 @@ #define STDIN_FILENO 0 #define STDOUT_FILENO 1 #define STDERR_FILENO 2 -// int _read(int file, const uint8_t *ptr, size_t len) { -// switch (file) -// { -// case STDIN_FILENO: -// default: -// errno = EBADF; -// return -1; -// } -// return 0; -// } -// -// extern UART_HandleTypeDef huart3; -// -// int _write(int file, const uint8_t *buf, size_t len) { -// switch (file) -// { -// case STDERR_FILENO: /* stderr */ -// case STDOUT_FILENO: /* stdout */ -// { -// // size_t bytesRemain = len; -// // while ((USBD_OK != CDC_Transmit_FS(buf, bytesRemain))); -// HAL_UART_Transmit(&huart3, buf, len, HAL_MAX_DELAY); -// break; -// } -// default: -// errno = EBADF; -// return -1; -// } -// return len; -// } - -// struct stat; -// int _fstat(int file, struct stat *st) { -// // st->st_mode = S_IFCHR; -// return 0; -// } -// -// int _getpid() { -// return 1; -// } -// - -#if defined(board4pi) || defined(due) +int _read(int file, const uint8_t *ptr, size_t len) { + switch (file) + { + case STDIN_FILENO: + default: + errno = EBADF; + return -1; + } + return 0; +} + + +int _write(int file, const uint8_t *buf, size_t len) { + switch (file) + { + case STDERR_FILENO: /* stderr */ + case STDOUT_FILENO: /* stdout */ + { + // size_t bytesRemain = len; + // while ((USBD_OK != CDC_Transmit_FS(buf, bytesRemain))); + break; + } + default: + errno = EBADF; + return -1; + } + return len; +} + + +#if defined(board4pi) bool main_cdc_enable(uint8_t port) { TRACE_INFO("CDC enabled\r\n"); return true; Index: src/motion_control_fixp32.c ================================================================== --- src/motion_control_fixp32.c +++ src/motion_control_fixp32.c @@ -3,24 +3,21 @@ #include "motion_control_fixp32.h" //#include //#include #include +#include "machine.h" #ifndef MACHINE_SIMULATION #include +#include "board.h" #endif #ifdef MACHINE_SIMULATION #include #endif -#include "gmf_config.h" - - -#include "machine.h" - enum { kSegNullMove, kSegLinearMove, kSegArcMove, kSegMovesCount Index: src/motion_planner_fixp32.c ================================================================== --- src/motion_planner_fixp32.c +++ src/motion_planner_fixp32.c @@ -337,30 +337,14 @@ return kMPlanErrNone; } -int mplan_planPrepare(void) -{ - return kMPlanErrUnimplemented; - -} -int mplan_planForward(void) -{ - return kMPlanErrUnimplemented; - -} -int mplan_planBackward(void) -{ - return kMPlanErrUnimplemented; - -} -int mplan_planVerify(void) -{ - return kMPlanErrUnimplemented; - -} +int mplan_planPrepare(void); +int mplan_planForward(void); +int mplan_planBackward(void); +int mplan_planVerify(void); int mplan_performPlanning(mplan_state_t* const self, mctrl_queue_t* const queue) { size_t queueUsed = mctrl_queue_collectGarbage(queue); DELETED src/sim/board.h Index: src/sim/board.h ================================================================== --- src/sim/board.h +++ src/sim/board.h @@ -1,31 +0,0 @@ -#ifndef BOARD_H -#define BOARD_H - -#include "sim.h" - -#define LASER_USART USART1 -#define ID_LASER_USART 0 - -#define PIN_LASER_PSU_IDX 0 -#define PIN_LASER_INTERLOCK_IDX 1 -#define PIN_LASER_LOCK_SENSE_IDX 2 -#define PIN_LASER_ALRM_SENSE_IDX 3 -#define PIN_LASER_EMBUT_SENSE_IDX 4 -#define PIN_LASER_PWM_IDX 5 -#define PIN_LASER_RXD_IDX 6 -#define PIN_LASER_TXD_IDX 7 - -#define LASER_LOCK_SENSE_FLAGS 0 -#define LASER_ALRM_SENSE_FLAGS 0 -#define LASER_EMBUT_SENSE_FLAGS 0 -#define LASER_PWM_FLAGS 0 - -#define PIN_LASER_RXD_FLAGS 0 -#define PIN_LASER_TXD_FLAGS 0 - -#define PWM_CHANNEL_LASER 0 - - - - -#endif DELETED src/sim/clock/clock.h Index: src/sim/clock/clock.h ================================================================== --- src/sim/clock/clock.h +++ src/sim/clock/clock.h @@ -1,13 +0,0 @@ -#ifndef CLOCK_H -#define CLOCK_H - -#include - -static inline void clock_delay_ms(uint32_t delay) {}; - -static inline uint32_t clock_getCpuFreq(void) { return 84000000; }; - -static inline void sysclk_enable_peripheral_clock(void* dummy) {}; -static inline uint32_t sysclk_get_peripheral_hz(void) {return 0;}; - -#endif //CLOCK_H DELETED src/sim/gpio/gpio.h Index: src/sim/gpio/gpio.h ================================================================== --- src/sim/gpio/gpio.h +++ src/sim/gpio/gpio.h @@ -1,10 +0,0 @@ -#ifndef GPIO_H -#define GPIO_H - -#include - -#define PIO_TYPE_PIO_OUTPUT_0 1 - -static inline void gpio_configure_pin(uint32_t idx, uint32_t flags) {}; - -#endif // GPIO_H DELETED src/sim/pdc/pdc.h Index: src/sim/pdc/pdc.h ================================================================== --- src/sim/pdc/pdc.h +++ src/sim/pdc/pdc.h @@ -1,48 +0,0 @@ -#ifndef PDC_H -#define PDC_H - -#include -#include "sim.h" - -#define PERIPH_PTCR_RXTEN 1 -#define PERIPH_PTCR_TXTEN 2 - -/*! \brief PDC data packet for transfer */ -typedef struct pdc_packet { - /** \brief Address for PDC transfer packet. - * The pointer to packet data start address. For pointer or next pointer - * register (_PR). - */ - uint32_t ul_addr; - /** \brief PDC transfer packet size. - * Size for counter or next counter register (_CR). The max value is - * 0xffff. - * The unit of size is based on peripheral data width, that is, data - * width that each time the peripheral transfers. - * E.g., size of PDC for USART is in number of bytes, but size of PDC - * for 16 bit SSC is in number of 16 bit word. - */ - uint32_t ul_size; -} pdc_packet_t; - -static inline void pdc_tx_init(Pdc *p_pdc, const pdc_packet_t * const p_packet, - const pdc_packet_t *const p_next_packet) {}; -static inline void pdc_rx_init(Pdc *p_pdc, const pdc_packet_t * const p_packet, - const pdc_packet_t * const p_next_packet) {}; -static inline void pdc_rx_clear_cnt(Pdc *p_pdc) {}; -static inline void pdc_enable_transfer(Pdc *p_pdc, uint32_t ul_controls) {}; -static inline void pdc_disable_transfer(Pdc *p_pdc, uint32_t ul_controls) {}; -static inline uint32_t pdc_read_status(Pdc *p_pdc) {return 0;}; -static inline uint32_t pdc_read_rx_ptr(Pdc *p_pdc) {return 0;}; -static inline uint32_t pdc_read_rx_counter(Pdc *p_pdc) {return 0;}; -static inline uint32_t pdc_read_tx_ptr(Pdc *p_pdc) {return 0;}; -static inline uint32_t pdc_read_tx_counter(Pdc *p_pdc) {return 0;}; -static inline uint32_t pdc_read_rx_next_ptr(Pdc *p_pdc) {return 0;}; -static inline uint32_t pdc_read_rx_next_counter(Pdc *p_pdc) {return 0;}; -static inline uint32_t pdc_read_tx_next_ptr(Pdc *p_pdc) {return 0;}; -static inline uint32_t pdc_read_tx_next_counter(Pdc *p_pdc) {return 0;}; - - - - -#endif // PDC_H DELETED src/sim/pwm/pwm.h Index: src/sim/pwm/pwm.h ================================================================== --- src/sim/pwm/pwm.h +++ src/sim/pwm/pwm.h @@ -1,60 +0,0 @@ -#ifndef PWM_H -#define PWM_H - -#include -#include "sim.h" - - -/** Definitions for PWM channel alignment */ -typedef enum { - PWM_ALIGN_LEFT = (0 << 8), /* The period is left aligned. */ - PWM_ALIGN_CENTER = (1 << 8) /* The period is center aligned. */ -} pwm_align_t; - -/** Definitions for PWM level */ -typedef enum { - PWM_LOW = 0, /* Low level */ - PWM_HIGH = 1, /* High level */ -} pwm_level_t; - -/** Input parameters when initializing PWM */ -typedef struct { - /** Frequency of clock A in Hz (set 0 to turn it off) */ - uint32_t ul_clka; - /** Frequency of clock B in Hz (set 0 to turn it off) */ - uint32_t ul_clkb; - /** Frequency of master clock in Hz */ - uint32_t ul_mck; -} pwm_clock_t; - - -/** Input parameters when configuring a PWM channel mode */ -typedef struct { - /** Channel number */ - uint32_t channel; - /** Channel prescaler */ - uint32_t ul_prescaler; - /** Channel alignment */ - pwm_align_t alignment; - /** Channel initial polarity */ - pwm_level_t polarity; - /** Duty Cycle Value */ - uint32_t ul_duty; - /** Period Cycle Value */ - uint32_t ul_period; -} pwm_channel_t; - - - - - -static inline uint32_t pwm_init(Pwm *p_pwm, pwm_clock_t *clock_config) {return 0;}; -static inline uint32_t pwm_channel_init(Pwm *p_pwm, pwm_channel_t *p_channel) {return 0;};; -static inline uint32_t pwm_channel_update_duty(Pwm *p_pwm, pwm_channel_t *p_channel, uint32_t ul_duty) {return 0;};; -static inline void pwm_channel_enable(Pwm *p_pwm, uint32_t ul_channel) {}; -static inline void pwm_channel_disable(Pwm *p_pwm, uint32_t ul_channel) {}; -static inline void pwm_channel_enable_interrupt(Pwm *p_pwm, uint32_t ul_event, uint32_t ul_fault) {}; -static inline void pwm_channel_disable_interrupt(Pwm *p_pwm, uint32_t ul_event, uint32_t ul_fault) {}; - - -#endif // PWM_H DELETED src/sim/serial/serial.h Index: src/sim/serial/serial.h ================================================================== --- src/sim/serial/serial.h +++ src/sim/serial/serial.h @@ -1,7 +0,0 @@ -#ifndef SERIAL_H -#define SERIAL_H - - - -#endif // SERIAL_H - DELETED src/sim/sim.c Index: src/sim/sim.c ================================================================== --- src/sim/sim.c +++ src/sim/sim.c @@ -1,4 +0,0 @@ -#include "sim.h" - - -Usart sim_usart1 = {0}; DELETED src/sim/sim.h Index: src/sim/sim.h ================================================================== --- src/sim/sim.h +++ src/sim/sim.h @@ -1,56 +0,0 @@ -#ifndef SIM_H -#define SIM_H - -#include - - -#define ID_PWM 0 - -#define PWM NULL - -#define USART1 (&sim_usart1) - - -// register bits -#define UART_SR_ENDRX 1 -#define UART_SR_TXBUFE 2 - -#define US_MR_PAR_NO 1 -#define US_MR_CHMODE_NORMAL 0 -#define US_MR_USART_MODE_Msk 0 -#define US_MR_USART_MODE_NORMAL 0 - -#define PWM_CMR_CPRE_CLKA 1 - - - - - -#define GPIO_PIN_SET(pin) () - -#define GPIO_PIN_CLR(pin) () - -#define GPIO_PIN_WRITE(pin, value) ((void*)pin) - -#define GPIO_PIN_GET(pin) () - - -struct Pdc_s; -typedef struct Pdc_S Pdc; - -struct Pwm_s; -typedef struct Pwm_S Pwm; - -struct Usart_s; -typedef struct Usart_s Usart; - - -struct Usart_s { - uint32_t US_MR; -}; - - - -extern Usart sim_usart1; - -#endif // SIM_H DELETED src/sim/usart/usart.h Index: src/sim/usart/usart.h ================================================================== --- src/sim/usart/usart.h +++ src/sim/usart/usart.h @@ -1,56 +0,0 @@ -#ifndef USART_H -#define USART_H - -#include "sim.h" - -/* Input parameters when initializing RS232 and similar modes. */ -typedef struct { - /* Set baud rate of the USART (unused in slave modes). */ - uint32_t baudrate; - - /* - * Number of bits, which should be one of the following: US_MR_CHRL_5_BIT, - * US_MR_CHRL_6_BIT, US_MR_CHRL_7_BIT, US_MR_CHRL_8_BIT or - * US_MR_MODE9. - */ - uint32_t char_length; - - /* - * Parity type, which should be one of the following: US_MR_PAR_EVEN, - * US_MR_PAR_ODD, US_MR_PAR_SPACE, US_MR_PAR_MARK, US_MR_PAR_NO - * or US_MR_PAR_MULTIDROP. - */ - uint32_t parity_type; - - /* - * Number of stop bits between two characters: US_MR_NBSTOP_1_BIT, - * US_MR_NBSTOP_1_5_BIT, US_MR_NBSTOP_2_BIT. - * \note US_MR_NBSTOP_1_5_BIT is supported in asynchronous modes only. - */ - uint32_t stop_bits; - - /* - * Run the channel in test mode, which should be one of following: - * US_MR_CHMODE_NORMAL, US_MR_CHMODE_AUTOMATIC, - * US_MR_CHMODE_LOCAL_LOOPBACK, US_MR_CHMODE_REMOTE_LOOPBACK. - */ - uint32_t channel_mode; - - /* Filter of IrDA mode, useless in other modes. */ - uint32_t irda_filter; -} sam_usart_opt_t; - - -static inline uint32_t usart_init_rs232(Usart *p_usart, const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck) {return 0;}; - -static inline void usart_enable_tx(Usart *p_usart) {}; -static inline void usart_disable_tx(Usart *p_usart) {}; -static inline void usart_enable_rx(Usart *p_usart) {}; -static inline void usart_disable_rx(Usart *p_usart) {}; - -static inline Pdc *usart_get_pdc_base(Usart *p_usart) {return NULL;}; -static inline uint32_t usart_get_status(Usart *p_usart) {return 0;}; -static inline uint32_t usart_putchar(Usart *p_usart, uint32_t c) {return 0;}; - - -#endif // USART_H DELETED src/sim/utility/trace.h Index: src/sim/utility/trace.h ================================================================== --- src/sim/utility/trace.h +++ src/sim/utility/trace.h DELETED src/sp200c.c Index: src/sp200c.c ================================================================== --- src/sp200c.c +++ src/sp200c.c @@ -1,311 +0,0 @@ - -#include "board.h" -#include "machine.h" -#include "clock/clock.h" -#include "serial/serial.h" -#include "usart/usart.h" -#include "pdc/pdc.h" -#include "pwm/pwm.h" -#include "gpio/gpio.h" -#include "utility/trace.h" - -#if defined(due) -#include "due.h" -#endif - -#include -#include - -#define RXBUF_COUNT 3 -#define TXBUF_COUNT 2 -#define RXBUF_LEN 64 -#define TXBUF_LEN 64 - -// 10kHz PWM -#define LASER_PWM_FREQUENCY 10000 -#define LASER_PWM_PERIOD 256 - - -// buffers for PDC DMA transfers -static uint8_t rxBuf[RXBUF_COUNT][RXBUF_LEN]; -static size_t rxBufRead = 0; -static size_t rxBufCurrentIndex = 0; -static uint8_t txBuf[TXBUF_COUNT][RXBUF_LEN]; -// static size_t txBufCount[TXBUF_COUNT] = {0,0}; -static size_t txBufNextIndex = 0; - - -// init buffers for peripheral DMA controller (PDC) -static void _initRxBuffers(void) -{ - pdc_packet_t const rxPacketA = {(intptr_t)rxBuf[0], RXBUF_LEN}; - pdc_packet_t rxPacketB = {(intptr_t)rxBuf[1], RXBUF_LEN}; - - Pdc* const pdc = usart_get_pdc_base(LASER_USART); - - pdc_rx_init(pdc, &rxPacketA, &rxPacketB); - pdc_enable_transfer(pdc, PERIPH_PTCR_RXTEN | PERIPH_PTCR_TXTEN); - - -} - - -// transmit a string via serial dma -static size_t _transmitCmd(const char* const buf, size_t const buflen) -{ - Pdc* const pdc = usart_get_pdc_base(LASER_USART); - - // uint32_t status = usart_get_status(LASER_USART); - - // bool txBufBusy[2] = {pdc_read_tx_ptr(pdc)}; - - // swap buffers via double xor - - pdc_packet_t const txPacketA = {(intptr_t)txBuf[txBufNextIndex], TXBUF_LEN}; - - size_t copyLen = MIN(buflen, TXBUF_LEN); - - memcpy(txBuf[txBufNextIndex], buf, copyLen); - - // spin while waiting for previous string to be sent - while (!(usart_get_status(LASER_USART) & UART_SR_TXBUFE)) - { - } - - // increment buffer index - txBufNextIndex = (txBufNextIndex + 1) % TXBUF_COUNT; - pdc_tx_init(pdc, &txPacketA, NULL); - - return copyLen; -} - -static size_t _transmitCmdImmediate(const char* const buf, size_t const buflen) -{ - Usart* usart = LASER_USART; - for (size_t i = 0; i < buflen; ++i) - usart_putchar(usart, buf[i]); - - - return buflen; -} - -static uint8_t laserLine[80] = {0}; -static size_t laserLineCount = 0; - -static void laser_processSerialInput(void) -{ - Pdc* const pdc = usart_get_pdc_base(LASER_USART); - - size_t rxCount = pdc_read_rx_counter(pdc); - - uint32_t status = usart_get_status(LASER_USART); - - bool currentBufferFilled = !!(status & UART_SR_ENDRX); - - uint8_t buf[2*RXBUF_LEN]; - size_t readBytes = 0; - - if (currentBufferFilled) - { - TRACE_INFO("got all the bytes\r\n") - // ENDRX flag is set to 1 when the receive buffer has been filled - // when that is the case, we know that the NEXT buffer became active - readBytes += RXBUF_LEN - rxBufRead; - memcpy(buf, rxBuf[rxBufCurrentIndex] + rxBufRead, readBytes); - - // swap our buffer pointer - size_t rxBufNextIndex = (rxBufCurrentIndex+1) % RXBUF_COUNT; - pdc_packet_t rxPacket = {(intptr_t)rxBuf[rxBufNextIndex], RXBUF_LEN}; - - pdc_rx_init(pdc, NULL, &rxPacket); - rxBufCurrentIndex = rxBufNextIndex; - rxBufRead = 0; - } - else if (rxCount - rxBufRead) - { - TRACE_INFO("got bytes\r\n") - readBytes += rxCount - rxBufRead; - memcpy(buf, rxBuf[rxBufCurrentIndex] + rxBufRead, readBytes); - rxBufRead += readBytes; - } - - // now that buf is filled, process - for (size_t i = 0; i < readBytes; ++i) - { - // output each line for debugging - switch (buf[i]) - { - case '\n': - laserLine[(laserLineCount) % 80] = 0; - TRACE_DEBUG("LASER SAID: %s", laserLine); - laserLineCount = 0; - break; - default: - laserLine[(laserLineCount++) % 80] = buf[i]; - break; - } - } - // echo everything received - Usart* usart = LASER_USART; - for (size_t i = 0; i < readBytes; ++i) - usart_putchar(usart, buf[i]); - -} - -static void laser_configurePorts(void) -{ - // switching relays - gpio_configure_pin(PIN_LASER_PSU_IDX, PIO_TYPE_PIO_OUTPUT_0); - gpio_configure_pin(PIN_LASER_INTERLOCK_IDX, PIO_TYPE_PIO_OUTPUT_0); - - // sense pins - gpio_configure_pin(PIN_LASER_LOCK_SENSE_IDX, LASER_LOCK_SENSE_FLAGS); - gpio_configure_pin(PIN_LASER_ALRM_SENSE_IDX, LASER_ALRM_SENSE_FLAGS); - gpio_configure_pin(PIN_LASER_EMBUT_SENSE_IDX, LASER_EMBUT_SENSE_FLAGS); - - // pwm - gpio_configure_pin(PIN_LASER_PWM_IDX, LASER_PWM_FLAGS); - -} - -/* Initialize PWM channel */ -/* Period is left-aligned */ -static pwm_channel_t laserPwmChannel = { - .alignment = PWM_ALIGN_LEFT, - .polarity = PWM_LOW, - .ul_prescaler = PWM_CMR_CPRE_CLKA, - .ul_period = LASER_PWM_PERIOD, - .ul_duty = 0, - .channel = PWM_CHANNEL_LASER, -}; - -static void laser_configurePwm(void) -{ - sysclk_enable_peripheral_clock(ID_PWM); - pwm_channel_disable(PWM, PWM_CHANNEL_LASER); - - /* Set PWM clock A as PWM_FREQUENCY*PERIOD_VALUE (clock B is not used) */ - pwm_clock_t clock_setting = { - .ul_clka = LASER_PWM_FREQUENCY * LASER_PWM_PERIOD, - .ul_clkb = 0, - .ul_mck = sysclk_get_cpu_hz() - }; - pwm_init(PWM, &clock_setting); - - - pwm_channel_init(PWM, &laserPwmChannel); - - - - pwm_channel_disable_interrupt(PWM, PWM_CHANNEL_LASER, 0); - - - - pwm_channel_enable(PWM, PWM_CHANNEL_LASER); - -} - -static void laser_configureSerial(void) -{ - // usart_serial_options_t serial_options = { - // .baudrate = 9600, - // .charlength = 8, - // .paritytype = US_MR_PAR_NO, - // .stopbits = false - // }; - sam_usart_opt_t usart_settings = { - .baudrate = 9600, - .char_length = 8, - .parity_type = US_MR_PAR_NO, - .stop_bits= false, - .channel_mode= US_MR_CHMODE_NORMAL - }; - - // Disable watchdog http://www.mikrocontroller.net/topic/382903#4378997 - // WDT->WDT_MR = WDT_MR_WDDIS; - // - // - // PMC->PMC_PCER0 |= 0x00020000; // Init von Kaj - // PIOA->PIO_PDR |= 0x00000C00; - // PIOA->PIO_OER |= 0x00000800; - // PIOA->PIO_ABSR &= ~0x00000C00; - // - // USART0->US_CR = 0x00000010; - // USART0->US_MR = 0x000008C0; - // USART0->US_BRGR = 46; - - - - /* Configure console UART. */ - sysclk_enable_peripheral_clock(ID_LASER_USART); - - usart_init_rs232(LASER_USART, &usart_settings, sysclk_get_peripheral_hz()); - - // set usart mode to not be fucked up (for some insane reason it is apparently inited in irda mode) - LASER_USART->US_MR = (LASER_USART->US_MR & ~US_MR_USART_MODE_Msk) | - US_MR_USART_MODE_NORMAL; - - - usart_enable_rx(LASER_USART); - usart_enable_tx(LASER_USART); - - /* Enable UART IRQ */ - // usart_enable_interrupt(LASER_USART, UART_IER_RXBUFF); - - /* Enable UART interrupt */ - // NVIC_EnableIRQ(USART0_IRQn); - - // init PDC - _initRxBuffers(); - - // configure GPIO - gpio_configure_pin(PIN_LASER_RXD_IDX, PIN_LASER_RXD_FLAGS); - gpio_configure_pin(PIN_LASER_TXD_IDX, PIN_LASER_TXD_FLAGS); - - // while (true) - // { - // while(!(LASER_USART->US_CSR & US_CSR_TXRDY)); - // LASER_USART->US_THR = 'x'; - // - // //while(!(USART0->US_CSR & US_CSR_TXEMPTY)); - // - // // delay(10000000); // ca. 1s warten - // } - // -} - -void laser_init(void) -{ - laser_configureSerial(); - laser_configurePorts(); - laser_configurePwm(); -} - -void laser_idle(void) -{ - laser_processSerialInput(); -} - -void laser_enableTargetingLaser(bool const en) -{ - const char* cmd = en ? "RL=1\r\n" : "RL=0\r\n"; - _transmitCmd(cmd, strlen(cmd)); -} - -void laser_enablePowerSupply(bool const en) -{ - GPIO_PIN_WRITE(PIN_LASER_PSU_IDX, en); -} - -void laser_enableInterlock(bool const en) -{ - GPIO_PIN_WRITE(PIN_LASER_INTERLOCK_IDX, en); -} - - -void laser_setBeamPowerPwm(fix16d16_t const pwm) -{ - uint32_t duty = (pwm*LASER_PWM_PERIOD) >> 16; - pwm_channel_update_duty(PWM, &laserPwmChannel, duty); -} - DELETED src/startup_sam3x.c Index: src/startup_sam3x.c ================================================================== --- src/startup_sam3x.c +++ src/startup_sam3x.c @@ -1,221 +0,0 @@ -/** - * \file - * - * \brief Startup file for SAM3X. - * - * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "exceptions.h" -#include "sam3xa.h" -#include "system_sam3x.h" - -/* Initialize segments */ -extern uint32_t _sfixed; -extern uint32_t _efixed; -extern uint32_t _etext; -extern uint32_t _srelocate; -extern uint32_t _erelocate; -extern uint32_t _szero; -extern uint32_t _ezero; -extern uint32_t _sstack; -extern uint32_t _estack; - -/** \cond DOXYGEN_SHOULD_SKIP_THIS */ -int main(void); -/** \endcond */ - -void __libc_init_array(void); - -/* Exception Table */ -__attribute__ ((section(".vectors"))) -IntFunc exception_table[] = { - - /* Configure Initial Stack Pointer, using linker-generated symbols */ - (IntFunc) (&_estack), - (void*) Reset_Handler, - - (void*) NMI_Handler, - (void*) HardFault_Handler, - (void*) MemManage_Handler, - (void*) BusFault_Handler, - (void*) UsageFault_Handler, - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) SVC_Handler, - (void*) DebugMon_Handler, - (void*) (0UL), /* Reserved */ - (void*) PendSV_Handler, - (void*) SysTick_Handler, - - /* Configurable interrupts */ - (void*) SUPC_Handler, /* 0 Supply Controller */ - (void*) RSTC_Handler, /* 1 Reset Controller */ - (void*) RTC_Handler, /* 2 Real Time Clock */ - (void*) RTT_Handler, /* 3 Real Time Timer */ - (void*) WDT_Handler, /* 4 Watchdog Timer */ - (void*) PMC_Handler, /* 5 PMC */ - (void*) EFC0_Handler, /* 6 EFC 0 */ - (void*) EFC1_Handler, /* 7 EFC 1 */ - (void*) UART_Handler, /* 8 UART */ -#ifdef _SAM3XA_SMC_INSTANCE_ - (void*) SMC_Handler, /* 9 SMC */ -#else - (void*) (0UL), /* 9 Reserved */ -#endif /* _SAM3XA_SMC_INSTANCE_ */ -#ifdef _SAM3XA_SDRAMC_INSTANCE_ - (void*) SDRAMC_Handler, /* 10 SDRAMC */ -#else - (void*) (0UL), /* 10 Reserved */ -#endif /* _SAM3XA_SDRAMC_INSTANCE_ */ - (void*) PIOA_Handler, /* 11 Parallel IO Controller A */ - (void*) PIOB_Handler, /* 12 Parallel IO Controller B */ -#ifdef _SAM3XA_PIOC_INSTANCE_ - (void*) PIOC_Handler, /* 13 Parallel IO Controller C */ -#else - (void*) (0UL), /* 13 Reserved */ -#endif /* _SAM3XA_PIOC_INSTANCE_ */ -#ifdef _SAM3XA_PIOD_INSTANCE_ - (void*) PIOD_Handler, /* 14 Parallel IO Controller D */ -#else - (void*) (0UL), /* 14 Reserved */ -#endif /* _SAM3XA_PIOD_INSTANCE_ */ -#ifdef _SAM3XA_PIOE_INSTANCE_ - (void*) PIOE_Handler, /* 15 Parallel IO Controller E */ -#else - (void*) (0UL), /* 15 Reserved */ -#endif /* _SAM3XA_PIOE_INSTANCE_ */ -#ifdef _SAM3XA_PIOF_INSTANCE_ - (void*) PIOF_Handler, /* 16 Parallel IO Controller F */ -#else - (void*) (0UL), /* 16 Reserved */ -#endif /* _SAM3XA_PIOF_INSTANCE_ */ - (void*) USART0_Handler, /* 17 USART 0 */ - (void*) USART1_Handler, /* 18 USART 1 */ - (void*) USART2_Handler, /* 19 USART 2 */ -#ifdef _SAM3XA_USART3_INSTANCE_ - (void*) USART3_Handler, /* 20 USART 3 */ -#else - (void*) (0UL), /* 20 Reserved */ -#endif /* _SAM3XA_USART3_INSTANCE_ */ - (void*) HSMCI_Handler, /* 21 MCI */ - (void*) TWI0_Handler, /* 22 TWI 0 */ - (void*) TWI1_Handler, /* 23 TWI 1 */ - (void*) SPI0_Handler, /* 24 SPI 0 */ -#ifdef _SAM3XA_SPI1_INSTANCE_ - (void*) SPI1_Handler, /* 25 SPI 1 */ -#else - (void*) (0UL), /* 25 Reserved */ -#endif /* _SAM3XA_SPI1_INSTANCE_ */ - (void*) SSC_Handler, /* 26 SSC */ - (void*) TC0_Handler, /* 27 Timer Counter 0 */ - (void*) TC1_Handler, /* 28 Timer Counter 1 */ - (void*) TC2_Handler, /* 29 Timer Counter 2 */ - (void*) TC3_Handler, /* 30 Timer Counter 3 */ - (void*) TC4_Handler, /* 31 Timer Counter 4 */ - (void*) TC5_Handler, /* 32 Timer Counter 5 */ -#ifdef _SAM3XA_TC2_INSTANCE_ - (void*) TC6_Handler, /* 33 Timer Counter 6 */ - (void*) TC7_Handler, /* 34 Timer Counter 7 */ - (void*) TC8_Handler, /* 35 Timer Counter 8 */ -#else - (void*) (0UL), /* 33 Reserved */ - (void*) (0UL), /* 34 Reserved */ - (void*) (0UL), /* 35 Reserved */ -#endif /* _SAM3XA_TC2_INSTANCE_ */ - (void*) PWM_Handler, /* 36 PWM */ - (void*) ADC_Handler, /* 37 ADC controller */ - (void*) DACC_Handler, /* 38 DAC controller */ - (void*) DMAC_Handler, /* 39 DMA Controller */ - (void*) UOTGHS_Handler, /* 40 USB OTG High Speed */ - (void*) TRNG_Handler, /* 41 True Random Number Generator */ -#ifdef _SAM3XA_EMAC_INSTANCE_ - (void*) EMAC_Handler, /* 42 Ethernet MAC */ -#else - (void*) (0UL), /* 42 Reserved */ -#endif /* _SAM3XA_EMAC_INSTANCE_ */ - (void*) CAN0_Handler, /* 43 CAN Controller 0 */ - (void*) CAN1_Handler /* 44 CAN Controller 1 */ -}; - -/* TEMPORARY PATCH FOR SCB */ -#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -/** - * \brief This is the code that gets called on processor reset. - * To initialize the device, and call the main() routine. - */ -void Reset_Handler(void) -{ - uint32_t *pSrc, *pDest; - - /* Initialize the relocate segment */ - pSrc = &_etext; - pDest = &_srelocate; - - if (pSrc != pDest) { - for (; pDest < &_erelocate;) { - *pDest++ = *pSrc++; - } - } - - /* Clear the zero segment */ - for (pDest = &_szero; pDest < &_ezero;) { - *pDest++ = 0; - } - - /* Set the vector table base address */ - pSrc = (uint32_t *) & _sfixed; - SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); - - if (((uint32_t) pSrc >= IRAM0_ADDR) && ((uint32_t) pSrc < NFC_RAM_ADDR)) { - SCB->VTOR |= 1 << SCB_VTOR_TBLBASE_Pos; - } - - /* Initialize the C library */ - __libc_init_array(); - - /* Branch to main function */ - main(); - - /* Infinite loop */ - while (1); -} Index: src/steptick.c ================================================================== --- src/steptick.c +++ src/steptick.c @@ -9,16 +9,13 @@ #include #include #include -#if defined(board4pi) || defined(due) - - #include "sysclk.h" - #include +#if defined(board4pi) +#include #endif - #include #include #include "motion_control_fixp32.h" #include "heater.h" @@ -27,27 +24,26 @@ #include "board.h" #define SLOWCTRL_IRQn USART3_IRQn #define SLOWCTRL_Handler USART3_Handler -#if defined(board4pi) || defined(due) +#if defined(board4pi) -#define gMicroSecTickCounter g_ul_ms_ticks - +extern volatile uint32_t g_ul_ms_ticks; // defined in cycle_counter.c +#define gMicrosecTickCounter g_ul_ms_ticks #elif defined(boardstm32f405h) volatile uint32_t gMicroSecTickCounter = 0; -#else - #error unknown board -#endif - void clock_delay_ms(const uint32_t delay) { const uint32_t tick = gMicroSecTickCounter; while (gMicroSecTickCounter - tick < delay) {}; } +#else + #error unknown board +#endif //void SysTick_Handler(void); uint32_t SysTick_Config(uint32_t ticks); uint32_t SysTick_GetPeriod(void); @@ -123,11 +119,11 @@ int gSysTickInterruptLength = 0; // position last given to slowTick (eg. heater control) routines -int32_t gSlowTickPositions[MC_NUM_AXES] = {MC_DEF(0,0,0,0,0,0)}; +int32_t gSlowTickPositions[MC_NUM_AXES] = {0,0,0,0,0}; int32_t gSlowTickThermistorADCVal[MACHINE_NUM_THERMISTOR_INPUTS] = {0,0,0,0}; int32_t gSlowTickThermistorADCMax = 0; static int32_t _slowTickThermistorADCVal[MACHINE_NUM_THERMISTOR_INPUTS] = {0,0,0,0}; static int32_t _slowTickThermistorADCMax = 0; Index: src/syscalls.c ================================================================== --- src/syscalls.c +++ src/syscalls.c @@ -103,16 +103,16 @@ extern int _lseek(int file, int ptr, int dir) { return 0; } -// extern void _exit(int status) -// { -// printf("Exiting with status %d.\n", status); -// -// for (;;); -// } +extern void _exit(int status) +{ + printf("Exiting with status %d.\n", status); + + for (;;); +} extern void _kill(int pid, int sig) { return; } DELETED src/system_sam3x.c Index: src/system_sam3x.c ================================================================== --- src/system_sam3x.c +++ src/system_sam3x.c @@ -1,222 +0,0 @@ -/** - * \file - * - * \brief Provides the low-level initialization functions that called - * on chip startup. - * - * Copyright (c) 2011 - 2013 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "system_sam3x.h" -#include "sam3xa.h" - -/* @cond 0 */ -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/* @endcond */ - -/* Clock settings (84MHz) */ -#define SYS_BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8)) -#define SYS_BOARD_PLLAR (CKGR_PLLAR_ONE \ - | CKGR_PLLAR_MULA(0xdUL) \ - | CKGR_PLLAR_PLLACOUNT(0x3fUL) \ - | CKGR_PLLAR_DIVA(0x1UL)) -#define SYS_BOARD_MCKR (PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK) - -/* Clock Definitions */ -#define SYS_UTMIPLL (480000000UL) /* UTMI PLL frequency */ - -#define SYS_CKGR_MOR_KEY_VALUE CKGR_MOR_KEY(0x37) /* Key to unlock MOR register */ - -/* FIXME: should be generated by sock */ -uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ; - -/** - * \brief Setup the microcontroller system. - * Initialize the System and update the SystemFrequency variable. - */ -void SystemInit(void) -{ - /* Set FWS according to SYS_BOARD_MCKR configuration */ - EFC0->EEFC_FMR = EEFC_FMR_FWS(4); - EFC1->EEFC_FMR = EEFC_FMR_FWS(4); - - /* Initialize main oscillator */ - if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)) { - PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT | - CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN; - while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) { - } - } - - /* Switch to 3-20MHz Xtal oscillator */ - PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT | - CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL; - - while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) { - } - PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | - PMC_MCKR_CSS_MAIN_CLK; - while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) { - } - - /* Initialize PLLA */ - PMC->CKGR_PLLAR = SYS_BOARD_PLLAR; - while (!(PMC->PMC_SR & PMC_SR_LOCKA)) { - } - - /* Switch to main clock */ - PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK; - while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) { - } - - /* Switch to PLLA */ - PMC->PMC_MCKR = SYS_BOARD_MCKR; - while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) { - } - - SystemCoreClock = CHIP_FREQ_CPU_MAX; -} - -void SystemCoreClockUpdate(void) -{ - /* Determine clock frequency according to clock register values */ - switch (PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) { - case PMC_MCKR_CSS_SLOW_CLK: /* Slow clock */ - if (SUPC->SUPC_SR & SUPC_SR_OSCSEL) { - SystemCoreClock = CHIP_FREQ_XTAL_32K; - } else { - SystemCoreClock = CHIP_FREQ_SLCK_RC; - } - break; - case PMC_MCKR_CSS_MAIN_CLK: /* Main clock */ - if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) { - SystemCoreClock = CHIP_FREQ_XTAL_12M; - } else { - SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ; - - switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) { - case CKGR_MOR_MOSCRCF_4_MHz: - break; - case CKGR_MOR_MOSCRCF_8_MHz: - SystemCoreClock *= 2U; - break; - case CKGR_MOR_MOSCRCF_12_MHz: - SystemCoreClock *= 3U; - break; - default: - break; - } - } - break; - case PMC_MCKR_CSS_PLLA_CLK: /* PLLA clock */ - case PMC_MCKR_CSS_UPLL_CLK: /* UPLL clock */ - if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) { - SystemCoreClock = CHIP_FREQ_XTAL_12M; - } else { - SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ; - - switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) { - case CKGR_MOR_MOSCRCF_4_MHz: - break; - case CKGR_MOR_MOSCRCF_8_MHz: - SystemCoreClock *= 2U; - break; - case CKGR_MOR_MOSCRCF_12_MHz: - SystemCoreClock *= 3U; - break; - default: - break; - } - } - if ((PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_PLLA_CLK) { - SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) >> - CKGR_PLLAR_MULA_Pos) + 1U); - SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk) >> - CKGR_PLLAR_DIVA_Pos)); - } else { - SystemCoreClock = SYS_UTMIPLL / 2U; - } - break; - } - - if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3) { - SystemCoreClock /= 3U; - } else { - SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> - PMC_MCKR_PRES_Pos); - } -} - -/** - * Initialize flash. - */ -void system_init_flash(uint32_t ul_clk) -{ - /* Set FWS for embedded Flash access according to operating frequency */ - if (ul_clk < CHIP_FREQ_FWS_0) { - EFC0->EEFC_FMR = EEFC_FMR_FWS(0); - EFC1->EEFC_FMR = EEFC_FMR_FWS(0); - } else if (ul_clk < CHIP_FREQ_FWS_1) { - EFC0->EEFC_FMR = EEFC_FMR_FWS(1); - EFC1->EEFC_FMR = EEFC_FMR_FWS(1); - } else if (ul_clk < CHIP_FREQ_FWS_2) { - EFC0->EEFC_FMR = EEFC_FMR_FWS(2); - EFC1->EEFC_FMR = EEFC_FMR_FWS(2); - } else if (ul_clk < CHIP_FREQ_FWS_3) { - EFC0->EEFC_FMR = EEFC_FMR_FWS(3); - EFC1->EEFC_FMR = EEFC_FMR_FWS(3); - } else if (ul_clk < CHIP_FREQ_FWS_4) { - EFC0->EEFC_FMR = EEFC_FMR_FWS(4); - EFC1->EEFC_FMR = EEFC_FMR_FWS(4); - } else { - EFC0->EEFC_FMR = EEFC_FMR_FWS(5); - EFC1->EEFC_FMR = EEFC_FMR_FWS(5); - } -} - -/* @cond 0 */ -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/* @endcond */ DELETED src/system_sam3x.h Index: src/system_sam3x.h ================================================================== --- src/system_sam3x.h +++ src/system_sam3x.h @@ -1,85 +0,0 @@ -/** - * \file - * - * \brief Provides the low-level initialization functions that called - * on chip startup. - * - * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef SYSTEM_SAM3X_H_INCLUDED -#define SYSTEM_SAM3X_H_INCLUDED - -/* @cond 0 */ -/**INDENT-OFF**/ -#ifdef __cplusplus -extern "C" { -#endif -/**INDENT-ON**/ -/* @endcond */ - -#include - -extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ - -/** - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -void SystemInit(void); - -/** - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -void SystemCoreClockUpdate(void); - -/** - * Initialize flash. - */ -void system_init_flash(uint32_t ul_clk); - -/* @cond 0 */ -/**INDENT-OFF**/ -#ifdef __cplusplus -} -#endif -/**INDENT-ON**/ -/* @endcond */ - -#endif /* SYSTEM_SAM3X_H_INCLUDED */ Index: stm32/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h ================================================================== --- stm32/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h +++ stm32/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h @@ -1,7491 +1,7491 @@ -/** - ****************************************************************************** - * @file stm32f405xx.h - * @author MCD Application Team - * @version V2.5.1 - * @date 28-June-2016 - * @brief CMSIS STM32F405xx Device Peripheral Access Layer Header File. - * - * This file contains: - * - Data structures and the address mapping for all peripherals - * - peripherals registers declarations and bits definition - * - Macros to access peripheral’s registers hardware - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f405xx - * @{ - */ - -#ifndef __STM32F405xx_H -#define __STM32F405xx_H - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ - -/** - * @brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ -#define __CM4_REV 0x0001U /*!< Core revision r0p1 */ -#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ -#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ -//#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1U /*!< FPU present */ - -/** - * @} - */ - -/** @addtogroup Peripheral_interrupt_number_definition - * @{ - */ - -/** - * @brief STM32F4XX Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ -typedef enum -{ -/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ -/****** STM32 specific Interrupt Numbers **********************************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ - TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ - RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ - DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ - DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ - DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ - DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ - DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ - DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ - ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ - CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ - CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ - TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ - TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ - TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ - TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ - TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ - DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ - FSMC_IRQn = 48, /*!< FSMC global Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ - TIM7_IRQn = 55, /*!< TIM7 global interrupt */ - DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ - DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ - DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ - DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ - DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ - CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ - CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ - CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ - CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ - OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ - DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ - DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ - DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ - USART6_IRQn = 71, /*!< USART6 global interrupt */ - I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ - I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ - OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ - OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ - OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ - OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ - HASH_RNG_IRQn = 80, /*!< Hash and RNG global interrupt */ - FPU_IRQn = 81 /*!< FPU global interrupt */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ -#include "system_stm32f4xx.h" -#include - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ - __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ - __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ - __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ - __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ - __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ - __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ - __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ - __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ - __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ - __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ - __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ - __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ - __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ - __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ - __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ - __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ - __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ - __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ - __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ - __IO uint32_t CDR; /*!< ADC common regular data register for dual - AND triple modes, Address offset: ADC1 base address + 0x308 */ -} ADC_Common_TypeDef; - - -/** - * @brief Controller Area Network TxMailBox - */ - -typedef struct -{ - __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ - __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ - __IO uint32_t TDLR; /*!< CAN mailbox data low register */ - __IO uint32_t TDHR; /*!< CAN mailbox data high register */ -} CAN_TxMailBox_TypeDef; - -/** - * @brief Controller Area Network FIFOMailBox - */ - -typedef struct -{ - __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ - __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ - __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ - __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ -} CAN_FIFOMailBox_TypeDef; - -/** - * @brief Controller Area Network FilterRegister - */ - -typedef struct -{ - __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ - __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ -} CAN_FilterRegister_TypeDef; - -/** - * @brief Controller Area Network - */ - -typedef struct -{ - __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ - __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ - __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ - __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ - __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ - __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ - __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ - __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ - uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ - CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ - CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ - uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ - __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ - __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ - uint32_t RESERVED2; /*!< Reserved, 0x208 */ - __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ - uint32_t RESERVED3; /*!< Reserved, 0x210 */ - __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ - uint32_t RESERVED4; /*!< Reserved, 0x218 */ - __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ - uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ - CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ -} CAN_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - uint8_t RESERVED0; /*!< Reserved, 0x05 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ -} CRC_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ - __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ - __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DMA stream x configuration register */ - __IO uint32_t NDTR; /*!< DMA stream x number of data register */ - __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ - __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ - __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ - __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ -} DMA_Stream_TypeDef; - -typedef struct -{ - __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ - __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ - __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ - __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ -} DMA_TypeDef; - - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ - __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ - __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ - __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ - __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ - __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ -} EXTI_TypeDef; - -/** - * @brief FLASH Registers - */ - -typedef struct -{ - __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ - __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ - __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ - __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ - __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ - __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */ - __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */ -} FLASH_TypeDef; - - -/** - * @brief Flexible Static Memory Controller - */ - -typedef struct -{ - __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ -} FSMC_Bank1_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank1E - */ - -typedef struct -{ - __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ -} FSMC_Bank1E_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank2 - */ - -typedef struct -{ - __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ - __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ - __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ - __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ - uint32_t RESERVED0; /*!< Reserved, 0x70 */ - __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ - uint32_t RESERVED1; /*!< Reserved, 0x78 */ - uint32_t RESERVED2; /*!< Reserved, 0x7C */ - __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ - __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ - __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ - __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ - uint32_t RESERVED3; /*!< Reserved, 0x90 */ - __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ -} FSMC_Bank2_3_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank4 - */ - -typedef struct -{ - __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ - __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ - __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ - __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ - __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ -} FSMC_Bank4_TypeDef; - - -/** - * @brief General Purpose I/O - */ - -typedef struct -{ - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ -} GPIO_TypeDef; - -/** - * @brief System configuration controller - */ - -typedef struct -{ - __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ - __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ - __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ - uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ - __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ -} SYSCFG_TypeDef; - -/** - * @brief Inter-integrated Circuit Interface - */ - -typedef struct -{ - __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ - __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ - __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ - __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */ - __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ - __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ - __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ - __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ - __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */ -} I2C_TypeDef; - -/** - * @brief Independent WATCHDOG - */ - -typedef struct -{ - __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ - __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ - __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ - __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ -} IWDG_TypeDef; - -/** - * @brief Power Control - */ - -typedef struct -{ - __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ - __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ -} PWR_TypeDef; - -/** - * @brief Reset and Clock Control - */ - -typedef struct -{ - __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ - __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ - __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ - __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ - __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ - __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ - __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ - uint32_t RESERVED0; /*!< Reserved, 0x1C */ - __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ - __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ - uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ - __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ - __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ - __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ - uint32_t RESERVED2; /*!< Reserved, 0x3C */ - __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ - __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ - uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ - __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ - __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ - __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ - uint32_t RESERVED4; /*!< Reserved, 0x5C */ - __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ - __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ - uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ - __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ - __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ - uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ - __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ - __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ - -} RCC_TypeDef; - -/** - * @brief Real-Time Clock - */ - -typedef struct -{ - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ - __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ - __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ - __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ - __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ - __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */ - __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */ - uint32_t RESERVED7; /*!< Reserved, 0x4C */ - __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ - __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ - __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ - __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ - __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ - __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ - __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ - __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ - __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ - __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ - __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ - __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ - __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ - __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ - __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ - __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ - __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ - __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ - __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ - __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ -} RTC_TypeDef; - - -/** - * @brief SD host Interface - */ - -typedef struct -{ - __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ - __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ - __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ - __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ - __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ - __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ - __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ - __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ - __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ - __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ - __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ - __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ - __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ - __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ - __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ - __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ - uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ - __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ - uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ - __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ -} SDIO_TypeDef; - -/** - * @brief Serial Peripheral Interface - */ - -typedef struct -{ - __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ - __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ - __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */ - __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ - __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ - __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ - __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ - __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ - __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ -} SPI_TypeDef; - -/** - * @brief TIM - */ - -typedef struct -{ - __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ - __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ - __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ - __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ - __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ - __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ - __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ - __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ - __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ - __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ - __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ - __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ - __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ -} TIM_TypeDef; - -/** - * @brief Universal Synchronous Asynchronous Receiver Transmitter - */ - -typedef struct -{ - __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ - __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ - __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ - __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ - __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ - __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ -} USART_TypeDef; - -/** - * @brief Window WATCHDOG - */ - -typedef struct -{ - __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ - __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ - __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ -} WWDG_TypeDef; - - -/** - * @brief RNG - */ - -typedef struct -{ - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ -} RNG_TypeDef; - - - -/** - * @brief __USB_OTG_Core_register - */ -typedef struct -{ - __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register Address offset : 0x00 */ - __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register Address offset : 0x04 */ - __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register Address offset : 0x08 */ - __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register Address offset : 0x0C */ - __IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset : 0x10 */ - __IO uint32_t GINTSTS; /*!< Core Interrupt Register Address offset : 0x14 */ - __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register Address offset : 0x18 */ - __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register Address offset : 0x1C */ - __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register Address offset : 0x20 */ - __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register Address offset : 0x24 */ - __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28 */ - __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset : 0x2C */ - uint32_t Reserved30[2]; /* Reserved Address offset : 0x30 */ - __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset : 0x38 */ - __IO uint32_t CID; /*!< User ID Register Address offset : 0x3C */ - uint32_t Reserved40[48]; /*!< Reserved Address offset : 0x40-0xFF */ - __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset : 0x100 */ - __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ -} -USB_OTG_GlobalTypeDef; - - - -/** - * @brief __device_Registers - */ -typedef struct -{ - __IO uint32_t DCFG; /*!< dev Configuration Register Address offset : 0x800 */ - __IO uint32_t DCTL; /*!< dev Control Register Address offset : 0x804 */ - __IO uint32_t DSTS; /*!< dev Status Register (RO) Address offset : 0x808 */ - uint32_t Reserved0C; /*!< Reserved Address offset : 0x80C */ - __IO uint32_t DIEPMSK; /* !< dev IN Endpoint Mask Address offset : 0x810 */ - __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask Address offset : 0x814 */ - __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg Address offset : 0x818 */ - __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask Address offset : 0x81C */ - uint32_t Reserved20; /*!< Reserved Address offset : 0x820 */ - uint32_t Reserved9; /*!< Reserved Address offset : 0x824 */ - __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register Address offset : 0x828 */ - __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register Address offset : 0x82C */ - __IO uint32_t DTHRCTL; /*!< dev thr Address offset : 0x830 */ - __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset : 0x834 */ - __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset : 0x838 */ - __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset : 0x83C */ - uint32_t Reserved40; /*!< dedicated EP mask Address offset : 0x840 */ - __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset : 0x844 */ - uint32_t Reserved44[15]; /*!< Reserved Address offset : 0x844-0x87C */ - __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset : 0x884 */ -} -USB_OTG_DeviceTypeDef; - - -/** - * @brief __IN_Endpoint-Specific_Register - */ -typedef struct -{ - __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ - uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */ - __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ - uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch */ - __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ - __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ - __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ - uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ -} -USB_OTG_INEndpointTypeDef; - - -/** - * @brief __OUT_Endpoint-Specific_Registers - */ -typedef struct -{ - __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/ - uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/ - __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/ - uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/ - __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/ - __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/ - uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/ -} -USB_OTG_OUTEndpointTypeDef; - - -/** - * @brief __Host_Mode_Register_Structures - */ -typedef struct -{ - __IO uint32_t HCFG; /* Host Configuration Register 400h*/ - __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/ - __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/ - uint32_t Reserved40C; /* Reserved 40Ch*/ - __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/ - __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/ - __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/ -} -USB_OTG_HostTypeDef; - - -/** - * @brief __Host_Channel_Specific_Registers - */ -typedef struct -{ - __IO uint32_t HCCHAR; - __IO uint32_t HCSPLT; - __IO uint32_t HCINT; - __IO uint32_t HCINTMSK; - __IO uint32_t HCTSIZ; - __IO uint32_t HCDMA; - uint32_t Reserved[2]; -} -USB_OTG_HostChannelTypeDef; - - -/** - * @brief Peripheral_memory_map - */ -#define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */ -#define CCMDATARAM_BASE 0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */ -#define SRAM1_BASE 0x20000000U /*!< SRAM1(112 KB) base address in the alias region */ -#define SRAM2_BASE 0x2001C000U /*!< SRAM2(16 KB) base address in the alias region */ -#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */ -#define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */ -#define FSMC_R_BASE 0xA0000000U /*!< FSMC registers base address */ -#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region */ -#define SRAM2_BB_BASE 0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region */ -#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */ -#define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */ -#define FLASH_END 0x080FFFFFU /*!< FLASH end address */ -#define CCMDATARAM_END 0x1000FFFFU /*!< CCM data RAM end address */ - -/* Legacy defines */ -#define SRAM_BASE SRAM1_BASE -#define SRAM_BB_BASE SRAM1_BB_BASE - - -/*!< Peripheral memory map */ -#define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) -#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U) -#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U) - -/*!< APB1 peripherals */ -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U) -#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U) -#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U) -#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U) -#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U) -#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800U) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U) -#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U) -#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U) -#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400U) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800U) -#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U) -#define UART5_BASE (APB1PERIPH_BASE + 0x5000U) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U) -#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U) -#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000U) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400U) - -/*!< APB2 peripherals */ -#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U) -#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U) -#define USART1_BASE (APB2PERIPH_BASE + 0x1000U) -#define USART6_BASE (APB2PERIPH_BASE + 0x1400U) -#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U) -#define ADC2_BASE (APB2PERIPH_BASE + 0x2100U) -#define ADC3_BASE (APB2PERIPH_BASE + 0x2200U) -#define ADC_BASE (APB2PERIPH_BASE + 0x2300U) -#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U) -#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U) -#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U) -#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U) -#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U) -#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U) - -/*!< AHB1 peripherals */ -#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U) -#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U) -#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U) -#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U) -#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U) -#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U) -#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U) -#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U) -#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U) -#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U) -#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U) -#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U) -#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U) -#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U) -#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U) -#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U) -#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U) -#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U) -#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U) -#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U) -#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U) -#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U) -#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U) -#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U) -#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U) -#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U) -#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U) -#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U) -#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U) -#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U) - -/*!< AHB2 peripherals */ -#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U) - -/*!< FSMC Bankx registers base address */ -#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000U) -#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104U) -#define FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060U) -#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0U) - -/* Debug MCU registers base address */ -#define DBGMCU_BASE 0xE0042000U - -/*!< USB registers base address */ -#define USB_OTG_HS_PERIPH_BASE 0x40040000U -#define USB_OTG_FS_PERIPH_BASE 0x50000000U - -#define USB_OTG_GLOBAL_BASE 0x000U -#define USB_OTG_DEVICE_BASE 0x800U -#define USB_OTG_IN_ENDPOINT_BASE 0x900U -#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U -#define USB_OTG_EP_REG_SIZE 0x20U -#define USB_OTG_HOST_BASE 0x400U -#define USB_OTG_HOST_PORT_BASE 0x440U -#define USB_OTG_HOST_CHANNEL_BASE 0x500U -#define USB_OTG_HOST_CHANNEL_SIZE 0x20U -#define USB_OTG_PCGCCTL_BASE 0xE00U -#define USB_OTG_FIFO_BASE 0x1000U -#define USB_OTG_FIFO_SIZE 0x1000U - -/** - * @} - */ - -/** @addtogroup Peripheral_declaration - * @{ - */ -#define TIM2 ((TIM_TypeDef *) TIM2_BASE) -#define TIM3 ((TIM_TypeDef *) TIM3_BASE) -#define TIM4 ((TIM_TypeDef *) TIM4_BASE) -#define TIM5 ((TIM_TypeDef *) TIM5_BASE) -#define TIM6 ((TIM_TypeDef *) TIM6_BASE) -#define TIM7 ((TIM_TypeDef *) TIM7_BASE) -#define TIM12 ((TIM_TypeDef *) TIM12_BASE) -#define TIM13 ((TIM_TypeDef *) TIM13_BASE) -#define TIM14 ((TIM_TypeDef *) TIM14_BASE) -#define RTC ((RTC_TypeDef *) RTC_BASE) -#define WWDG ((WWDG_TypeDef *) WWDG_BASE) -#define IWDG ((IWDG_TypeDef *) IWDG_BASE) -#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE) -#define SPI2 ((SPI_TypeDef *) SPI2_BASE) -#define SPI3 ((SPI_TypeDef *) SPI3_BASE) -#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE) -#define USART2 ((USART_TypeDef *) USART2_BASE) -#define USART3 ((USART_TypeDef *) USART3_BASE) -#define UART4 ((USART_TypeDef *) UART4_BASE) -#define UART5 ((USART_TypeDef *) UART5_BASE) -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#define I2C2 ((I2C_TypeDef *) I2C2_BASE) -#define I2C3 ((I2C_TypeDef *) I2C3_BASE) -#define CAN1 ((CAN_TypeDef *) CAN1_BASE) -#define CAN2 ((CAN_TypeDef *) CAN2_BASE) -#define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC ((DAC_TypeDef *) DAC_BASE) -#define TIM1 ((TIM_TypeDef *) TIM1_BASE) -#define TIM8 ((TIM_TypeDef *) TIM8_BASE) -#define USART1 ((USART_TypeDef *) USART1_BASE) -#define USART6 ((USART_TypeDef *) USART6_BASE) -#define ADC ((ADC_Common_TypeDef *) ADC_BASE) -#define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#define ADC2 ((ADC_TypeDef *) ADC2_BASE) -#define ADC3 ((ADC_TypeDef *) ADC3_BASE) -#define SDIO ((SDIO_TypeDef *) SDIO_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) -#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) -#define EXTI ((EXTI_TypeDef *) EXTI_BASE) -#define TIM9 ((TIM_TypeDef *) TIM9_BASE) -#define TIM10 ((TIM_TypeDef *) TIM10_BASE) -#define TIM11 ((TIM_TypeDef *) TIM11_BASE) -#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) -#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) -#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) -#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) -#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) -#define CRC ((CRC_TypeDef *) CRC_BASE) -#define RCC ((RCC_TypeDef *) RCC_BASE) -#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) -#define DMA1 ((DMA_TypeDef *) DMA1_BASE) -#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) -#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) -#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) -#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) -#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) -#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) -#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) -#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) -#define DMA2 ((DMA_TypeDef *) DMA2_BASE) -#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) -#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) -#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) -#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) -#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) -#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) -#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) -#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) -#define RNG ((RNG_TypeDef *) RNG_BASE) -#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) -#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) -#define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE) -#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) - -#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) - -#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) -#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE) - -/** - * @} - */ - -/** @addtogroup Exported_constants - * @{ - */ - - /** @addtogroup Peripheral_Registers_Bits_Definition - * @{ - */ - -/******************************************************************************/ -/* Peripheral Registers_Bits_Definition */ -/******************************************************************************/ - -/******************************************************************************/ -/* */ -/* Analog to Digital Converter */ -/* */ -/******************************************************************************/ -/******************** Bit definition for ADC_SR register ********************/ -#define ADC_SR_AWD 0x00000001U /*!
© COPYRIGHT(c) 2016 STMicroelectronics
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f405xx + * @{ + */ + +#ifndef __STM32F405xx_H +#define __STM32F405xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001U /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ +// #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32F4XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FSMC_IRQn = 48, /*!< FSMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + HASH_RNG_IRQn = 80, /*!< Hash and RNG global interrupt */ + FPU_IRQn = 81 /*!< FPU global interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32f4xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ + __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ + __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ + __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ + __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ + __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ + __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual + AND triple modes, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +} CAN_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ +} DMA_TypeDef; + + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ + __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ + __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ + __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ + __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ + __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */ + __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */ +} FLASH_TypeDef; + + +/** + * @brief Flexible Static Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FSMC_Bank1_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FSMC_Bank1E_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank2 + */ + +typedef struct +{ + __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ + __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ + __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ + __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ + uint32_t RESERVED0; /*!< Reserved, 0x70 */ + __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ + uint32_t RESERVED1; /*!< Reserved, 0x78 */ + uint32_t RESERVED2; /*!< Reserved, 0x7C */ + __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + uint32_t RESERVED3; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ +} FSMC_Bank2_3_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank4 + */ + +typedef struct +{ + __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ + __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ + __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ + __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ + __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ +} FSMC_Bank4_TypeDef; + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ +} GPIO_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ + __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */ + __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ + __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ + __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ + __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ + __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ +} IWDG_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ + __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, 0x3C */ + __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, 0x5C */ + __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ + __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ + __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ + __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ + +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */ + uint32_t RESERVED7; /*!< Reserved, 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ +} RTC_TypeDef; + + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ + __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ + __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ +} SDIO_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** + * @brief RNG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + + + +/** + * @brief __USB_OTG_Core_register + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register Address offset : 0x00 */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register Address offset : 0x04 */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register Address offset : 0x08 */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register Address offset : 0x0C */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset : 0x10 */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register Address offset : 0x14 */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register Address offset : 0x18 */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register Address offset : 0x1C */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register Address offset : 0x20 */ + __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register Address offset : 0x24 */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28 */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset : 0x2C */ + uint32_t Reserved30[2]; /* Reserved Address offset : 0x30 */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset : 0x38 */ + __IO uint32_t CID; /*!< User ID Register Address offset : 0x3C */ + uint32_t Reserved40[48]; /*!< Reserved Address offset : 0x40-0xFF */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset : 0x100 */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ +} +USB_OTG_GlobalTypeDef; + + + +/** + * @brief __device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register Address offset : 0x800 */ + __IO uint32_t DCTL; /*!< dev Control Register Address offset : 0x804 */ + __IO uint32_t DSTS; /*!< dev Status Register (RO) Address offset : 0x808 */ + uint32_t Reserved0C; /*!< Reserved Address offset : 0x80C */ + __IO uint32_t DIEPMSK; /* !< dev IN Endpoint Mask Address offset : 0x810 */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask Address offset : 0x814 */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg Address offset : 0x818 */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask Address offset : 0x81C */ + uint32_t Reserved20; /*!< Reserved Address offset : 0x820 */ + uint32_t Reserved9; /*!< Reserved Address offset : 0x824 */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register Address offset : 0x828 */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register Address offset : 0x82C */ + __IO uint32_t DTHRCTL; /*!< dev thr Address offset : 0x830 */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset : 0x834 */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset : 0x838 */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset : 0x83C */ + uint32_t Reserved40; /*!< dedicated EP mask Address offset : 0x840 */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset : 0x844 */ + uint32_t Reserved44[15]; /*!< Reserved Address offset : 0x844-0x87C */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset : 0x884 */ +} +USB_OTG_DeviceTypeDef; + + +/** + * @brief __IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ +} +USB_OTG_INEndpointTypeDef; + + +/** + * @brief __OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/ + uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/ + __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/ + uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/ + __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/ + __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/ + uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/ +} +USB_OTG_OUTEndpointTypeDef; + + +/** + * @brief __Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /* Host Configuration Register 400h*/ + __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/ + __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/ + uint32_t Reserved40C; /* Reserved 40Ch*/ + __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/ + __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/ + __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/ +} +USB_OTG_HostTypeDef; + + +/** + * @brief __Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; + __IO uint32_t HCSPLT; + __IO uint32_t HCINT; + __IO uint32_t HCINTMSK; + __IO uint32_t HCTSIZ; + __IO uint32_t HCDMA; + uint32_t Reserved[2]; +} +USB_OTG_HostChannelTypeDef; + + +/** + * @brief Peripheral_memory_map + */ +#define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */ +#define CCMDATARAM_BASE 0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */ +#define SRAM1_BASE 0x20000000U /*!< SRAM1(112 KB) base address in the alias region */ +#define SRAM2_BASE 0x2001C000U /*!< SRAM2(16 KB) base address in the alias region */ +#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */ +#define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */ +#define FSMC_R_BASE 0xA0000000U /*!< FSMC registers base address */ +#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region */ +#define SRAM2_BB_BASE 0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */ +#define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */ +#define FLASH_END 0x080FFFFFU /*!< FLASH end address */ +#define CCMDATARAM_END 0x1000FFFFU /*!< CCM data RAM end address */ + +/* Legacy defines */ +#define SRAM_BASE SRAM1_BASE +#define SRAM_BB_BASE SRAM1_BB_BASE + + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U) +#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U) +#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800U) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U) +#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U) +#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400U) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800U) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000U) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000U) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400U) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U) +#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U) +#define USART1_BASE (APB2PERIPH_BASE + 0x1000U) +#define USART6_BASE (APB2PERIPH_BASE + 0x1400U) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2100U) +#define ADC3_BASE (APB2PERIPH_BASE + 0x2200U) +#define ADC_BASE (APB2PERIPH_BASE + 0x2300U) +#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U) +#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U) +#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U) +#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U) + +/*!< AHB1 peripherals */ +#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U) +#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U) +#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U) +#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U) +#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U) +#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U) +#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U) +#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U) +#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U) +#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U) +#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U) +#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U) +#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U) +#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U) +#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U) +#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U) +#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U) +#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U) +#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U) +#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U) +#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U) +#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U) +#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U) +#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U) +#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U) +#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U) +#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U) + +/*!< AHB2 peripherals */ +#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U) + +/*!< FSMC Bankx registers base address */ +#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000U) +#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104U) +#define FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060U) +#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0U) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE 0xE0042000U + +/*!< USB registers base address */ +#define USB_OTG_HS_PERIPH_BASE 0x40040000U +#define USB_OTG_FS_PERIPH_BASE 0x50000000U + +#define USB_OTG_GLOBAL_BASE 0x000U +#define USB_OTG_DEVICE_BASE 0x800U +#define USB_OTG_IN_ENDPOINT_BASE 0x900U +#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U +#define USB_OTG_EP_REG_SIZE 0x20U +#define USB_OTG_HOST_BASE 0x400U +#define USB_OTG_HOST_PORT_BASE 0x440U +#define USB_OTG_HOST_CHANNEL_BASE 0x500U +#define USB_OTG_HOST_CHANNEL_SIZE 0x20U +#define USB_OTG_PCGCCTL_BASE 0xE00U +#define USB_OTG_FIFO_BASE 0x1000U +#define USB_OTG_FIFO_SIZE 0x1000U + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define CAN2 ((CAN_TypeDef *) CAN2_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define ADC ((ADC_Common_TypeDef *) ADC_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) +#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) +#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) +#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) +#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) +#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) +#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) +#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) +#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) +#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) +#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) +#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) +#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) +#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) +#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) +#define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE) +#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) +#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD 0x00000001U /*! - #ifdef __cplusplus extern "C" { #endif /** @addtogroup STM32F4xx_System_Includes Index: stm32/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c ================================================================== --- stm32/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c +++ stm32/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c @@ -242,12 +242,12 @@ * Counter is in free running mode to generate periodic interrupts. * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ -uint32_t SysTick_Config(uint32_t TicksNumb); - +extern uint32_t SysTick_Config(uint32_t TicksNumb); + uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { return SysTick_Config(TicksNumb); } /** Index: stm32/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c ================================================================== --- stm32/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c +++ stm32/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c @@ -72,11 +72,10 @@ ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal.h" -#include "usbd_conf.h" /** @addtogroup STM32F4xx_HAL_Driver * @{ */ @@ -295,11 +294,10 @@ * @param hpcd: PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) { - USBD_DbgLog("HAL_PCD_Start()"); __HAL_LOCK(hpcd); USB_DevConnect (hpcd->Instance); __HAL_PCD_ENABLE(hpcd); __HAL_UNLOCK(hpcd); return HAL_OK; @@ -325,11 +323,10 @@ * @param hpcd: PCD handle * @retval HAL status */ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { - USBD_DbgLog("HAL_PCD_IRQHandler: %d", USB_ReadInterrupts(hpcd->Instance)); USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; uint32_t i = 0U, ep_intr = 0U, epint = 0U, epnum = 0U; uint32_t fifoemptymsk = 0U, temp = 0U; USB_OTG_EPTypeDef *ep; uint32_t hclk = 180000000; @@ -945,11 +942,10 @@ * @param ep_type: endpoint type * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) { - USBD_DbgLog("HAL_PCD_EP_Open()"); HAL_StatusTypeDef ret = HAL_OK; USB_OTG_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) { @@ -1019,11 +1015,10 @@ * @param len: amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { - USBD_DbgLog("HAL_PCD_EP_Receive()"); USB_OTG_EPTypeDef *ep; ep = &hpcd->OUT_ep[ep_addr & 0x7FU]; /*setup and start the Xfer */ @@ -1111,11 +1106,10 @@ * @param ep_addr: endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { - USBD_DbgLog("HAL_PCD_EP_SetStall()"); USB_OTG_EPTypeDef *ep; if ((0x80U & ep_addr) == 0x80U) { ep = &hpcd->IN_ep[ep_addr & 0x7FU]; Index: stm32/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c ================================================================== --- stm32/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c +++ stm32/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c @@ -55,11 +55,10 @@ ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal.h" -#include "usbd_conf.h" /** @addtogroup STM32F4xx_LL_USB_DRIVER * @{ */ @@ -202,11 +201,10 @@ * the configuration information for the specified USBx peripheral. * @retval HAL status */ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { - USBD_DbgLog("USB_DevInit()"); uint32_t i = 0U; /*Activate VBUS Sensing B */ #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ defined(STM32F412Rx) || defined(STM32F412Cx) @@ -346,11 +344,10 @@ 15 means Flush all Tx FIFOs * @retval HAL status */ HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num ) { - USBD_DbgLog("USB_FlushTxFifo()"); uint32_t count = 0U; USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)( num << 6)); do @@ -371,11 +368,10 @@ * @param USBx : Selected device * @retval HAL status */ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) { - USBD_DbgLog("USB_FlushRxFifo()"); uint32_t count = 0U; USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; do Index: stm32/STM32_USB_Device_Library/Core/Src/usbd_core.c ================================================================== --- stm32/STM32_USB_Device_Library/Core/Src/usbd_core.c +++ stm32/STM32_USB_Device_Library/Core/Src/usbd_core.c @@ -93,11 +93,10 @@ * @param id: Low level core index * @retval None */ USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id) { - USBD_DbgLog("USBD_Init()"); /* Check whether the USB Host handle is valid */ if(pdev == NULL) { USBD_ErrLog("Invalid Device handle"); return USBD_FAIL; @@ -179,11 +178,10 @@ * @param pdev: Device Handle * @retval USBD Status */ USBD_StatusTypeDef USBD_Start (USBD_HandleTypeDef *pdev) { - USBD_DbgLog("USBD_Start()"); /* Start the low level driver */ USBD_LL_Start(pdev); return USBD_OK; @@ -262,11 +260,10 @@ * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup) { - USBD_DbgLog("USBD_LL_SetupStage()"); USBD_ParseSetupRequest(&pdev->request, psetup); pdev->ep0_state = USBD_EP0_SETUP; pdev->ep0_data_len = pdev->request.wLength; @@ -415,12 +412,11 @@ * @retval status */ USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev) { - USBD_DbgLog("USBD_LL_Reset()"); - /* Open EP0 OUT */ + /* Open EP0 OUT */ USBD_LL_OpenEP(pdev, 0x00, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); Index: stm32/boards/stm32f405/STM32F405RGTx_FLASH.ld ================================================================== --- stm32/boards/stm32f405/STM32F405RGTx_FLASH.ld +++ stm32/boards/stm32f405/STM32F405RGTx_FLASH.ld @@ -52,12 +52,12 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = 0x20020000; /* end of RAM */ /* Generate a link error if heap and stack don't fit into RAM */ -_Min_Heap_Size = 0x2000; /* required amount of heap (8k)*/ -_Min_Stack_Size = 0x4000; /* required amount of stack (16k)*/ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ /* Specify the memory areas */ MEMORY { RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K @@ -100,51 +100,37 @@ *(.rodata) /* .rodata sections (constants, strings, etc.) */ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ . = ALIGN(4); } >FLASH - .ARM.extab : { - . = ALIGN(4); - *(.ARM.extab* .gnu.linkonce.armextab.*) - . = ALIGN(4); - } >FLASH - - d.ARM : { - . = ALIGN(4); + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; - . = ALIGN(4); - } >FLASH + } >FLASH .preinit_array : { - . = ALIGN(4); PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); - . = ALIGN(4); } >FLASH - .init_array : { - . = ALIGN(4); PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array*)) PROVIDE_HIDDEN (__init_array_end = .); - . = ALIGN(4); } >FLASH .fini_array : { - . = ALIGN(4); PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) KEEP (*(.fini_array*)) PROVIDE_HIDDEN (__fini_array_end = .); - . = ALIGN(4); - } >FLASH + } >FLASH /* used by the startup to initialize data */ _sidata = LOADADDR(.data); /* Initialized data sections goes into RAM, load LMA copy after code */ @@ -212,13 +198,11 @@ /DISCARD/ : { libc.a ( * ) libm.a ( * ) libgcc.a ( * ) - libnosys.a ( * ) - libg.a ( * ) } .ARM.attributes 0 : { *(.ARM.attributes) } } ADDED stm32/boards/stm32f405/main.h Index: stm32/boards/stm32f405/main.h ================================================================== --- stm32/boards/stm32f405/main.h +++ stm32/boards/stm32f405/main.h @@ -0,0 +1,131 @@ +/** + ****************************************************************************** + * File Name : main.h + * Description : This file contains the common defines of the application + ****************************************************************************** + * + * Copyright (c) 2016 STMicroelectronics International N.V. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted, provided that the following conditions are met: + * + * 1. Redistribution of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of other + * contributors to this software may be used to endorse or promote products + * derived from this software without specific written permission. + * 4. This software, including modifications and/or derivative works of this + * software, must execute solely and exclusively on microcontroller or + * microprocessor devices manufactured by or for STMicroelectronics. + * 5. Redistribution and use of this software other than as permitted under + * this license is void and will automatically terminate your rights under + * this license. + * + * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY + * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT + * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + /* Includes ------------------------------------------------------------------*/ + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private define ------------------------------------------------------------*/ + +#define X_STEP_Pin GPIO_PIN_0 +#define X_STEP_GPIO_Port GPIOC +#define Y_STEP_Pin GPIO_PIN_1 +#define Y_STEP_GPIO_Port GPIOC +#define Z_STEP_Pin GPIO_PIN_2 +#define Z_STEP_GPIO_Port GPIOC +#define X_DIR_Pin GPIO_PIN_3 +#define X_DIR_GPIO_Port GPIOC +#define BUT_Pin GPIO_PIN_0 +#define BUT_GPIO_Port GPIOA +#define LASER_POWER_MONITOR_Pin GPIO_PIN_1 +#define LASER_POWER_MONITOR_GPIO_Port GPIOA +#define DIODE_CURRENT_MONITOR_Pin GPIO_PIN_2 +#define DIODE_CURRENT_MONITOR_GPIO_Port GPIOA +#define LASER_POWER_Pin GPIO_PIN_4 +#define LASER_POWER_GPIO_Port GPIOA +#define ALRM_SENSE_Pin GPIO_PIN_5 +#define ALRM_SENSE_GPIO_Port GPIOA +#define LLOCK_SENSE_Pin GPIO_PIN_6 +#define LLOCK_SENSE_GPIO_Port GPIOA +#define EMISSION_SENSE_Pin GPIO_PIN_7 +#define EMISSION_SENSE_GPIO_Port GPIOA +#define USB_P_Pin GPIO_PIN_4 +#define USB_P_GPIO_Port GPIOC +#define Y_DIR_Pin GPIO_PIN_5 +#define Y_DIR_GPIO_Port GPIOC +#define X_LIM_POS_Pin GPIO_PIN_0 +#define X_LIM_POS_GPIO_Port GPIOB +#define X_LIM_NEG_Pin GPIO_PIN_1 +#define X_LIM_NEG_GPIO_Port GPIOB +#define Z_LIM_NEG_Pin GPIO_PIN_12 +#define Z_LIM_NEG_GPIO_Port GPIOB +#define Z_LIM_POS_Pin GPIO_PIN_15 +#define Z_LIM_POS_GPIO_Port GPIOB +#define Z_DIR_Pin GPIO_PIN_6 +#define Z_DIR_GPIO_Port GPIOC +#define X_EN_Pin GPIO_PIN_7 +#define X_EN_GPIO_Port GPIOC +#define Y_EN_Pin GPIO_PIN_8 +#define Y_EN_GPIO_Port GPIOC +#define Z_EN_Pin GPIO_PIN_9 +#define Z_EN_GPIO_Port GPIOC +#define MOTOR_PSU_Pin GPIO_PIN_8 +#define MOTOR_PSU_GPIO_Port GPIOA +#define MOTOR_PWR_Pin GPIO_PIN_9 +#define MOTOR_PWR_GPIO_Port GPIOA +#define LASER_KEY_Pin GPIO_PIN_10 +#define LASER_KEY_GPIO_Port GPIOA +#define LASER_PSU_Pin GPIO_PIN_10 +#define LASER_PSU_GPIO_Port GPIOC +#define DISC_Pin GPIO_PIN_11 +#define DISC_GPIO_Port GPIOC +#define LED_Pin GPIO_PIN_12 +#define LED_GPIO_Port GPIOC +#define Y_LIM_POS_Pin GPIO_PIN_5 +#define Y_LIM_POS_GPIO_Port GPIOB +#define Z_REF_Pin GPIO_PIN_6 +#define Z_REF_GPIO_Port GPIOB +#define Y_REF_Pin GPIO_PIN_7 +#define Y_REF_GPIO_Port GPIOB +#define Y_LIM_NEG_Pin GPIO_PIN_8 +#define Y_LIM_NEG_GPIO_Port GPIOB +#define X_REF_Pin GPIO_PIN_9 +#define X_REF_GPIO_Port GPIOB +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +/** + * @} + */ + +/** + * @} +*/ + +#endif /* __MAIN_H */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ADDED stm32/boards/stm32f405/mxconstants.h Index: stm32/boards/stm32f405/mxconstants.h ================================================================== --- stm32/boards/stm32f405/mxconstants.h +++ stm32/boards/stm32f405/mxconstants.h @@ -0,0 +1,121 @@ +/** + ****************************************************************************** + * File Name : mxconstants.h + * Description : This file contains the common defines of the application + ****************************************************************************** + * + * COPYRIGHT(c) 2016 STMicroelectronics + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MXCONSTANT_H +#define __MXCONSTANT_H + /* Includes ------------------------------------------------------------------*/ + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private define ------------------------------------------------------------*/ + +#define X_STEP_Pin GPIO_PIN_0 +#define X_STEP_GPIO_Port GPIOC +#define Y_STEP_Pin GPIO_PIN_1 +#define Y_STEP_GPIO_Port GPIOC +#define Z_STEP_Pin GPIO_PIN_2 +#define Z_STEP_GPIO_Port GPIOC +#define X_DIR_Pin GPIO_PIN_3 +#define X_DIR_GPIO_Port GPIOC +#define BUT_Pin GPIO_PIN_0 +#define BUT_GPIO_Port GPIOA +#define LASER_POWER_MONITOR_Pin GPIO_PIN_1 +#define LASER_POWER_MONITOR_GPIO_Port GPIOA +#define DIODE_CURRENT_MONITOR_Pin GPIO_PIN_2 +#define DIODE_CURRENT_MONITOR_GPIO_Port GPIOA +#define LASER_POWER_Pin GPIO_PIN_4 +#define LASER_POWER_GPIO_Port GPIOA +#define ALRM_SENSE_Pin GPIO_PIN_5 +#define ALRM_SENSE_GPIO_Port GPIOA +#define LLOCK_SENSE_Pin GPIO_PIN_6 +#define LLOCK_SENSE_GPIO_Port GPIOA +#define EMISSION_SENSE_Pin GPIO_PIN_7 +#define EMISSION_SENSE_GPIO_Port GPIOA +#define USB_P_Pin GPIO_PIN_4 +#define USB_P_GPIO_Port GPIOC +#define Y_DIR_Pin GPIO_PIN_5 +#define Y_DIR_GPIO_Port GPIOC +#define X_LIM_POS_Pin GPIO_PIN_0 +#define X_LIM_POS_GPIO_Port GPIOB +#define X_LIM_NEG_Pin GPIO_PIN_1 +#define X_LIM_NEG_GPIO_Port GPIOB +#define Z_LIM_NEG_Pin GPIO_PIN_12 +#define Z_LIM_NEG_GPIO_Port GPIOB +#define Z_LIM_POS_Pin GPIO_PIN_15 +#define Z_LIM_POS_GPIO_Port GPIOB +#define Z_DIR_Pin GPIO_PIN_6 +#define Z_DIR_GPIO_Port GPIOC +#define X_EN_Pin GPIO_PIN_7 +#define X_EN_GPIO_Port GPIOC +#define Y_EN_Pin GPIO_PIN_8 +#define Y_EN_GPIO_Port GPIOC +#define Z_EN_Pin GPIO_PIN_9 +#define Z_EN_GPIO_Port GPIOC +#define MOTOR_PSU_Pin GPIO_PIN_8 +#define MOTOR_PSU_GPIO_Port GPIOA +#define MOTOR_PWR_Pin GPIO_PIN_9 +#define MOTOR_PWR_GPIO_Port GPIOA +#define LASER_KEY_Pin GPIO_PIN_10 +#define LASER_KEY_GPIO_Port GPIOA +#define LASER_PSU_Pin GPIO_PIN_10 +#define LASER_PSU_GPIO_Port GPIOC +#define DISC_Pin GPIO_PIN_11 +#define DISC_GPIO_Port GPIOC +#define LED_Pin GPIO_PIN_12 +#define LED_GPIO_Port GPIOC +#define Y_LIM_POS_Pin GPIO_PIN_5 +#define Y_LIM_POS_GPIO_Port GPIOB +#define Z_REF_Pin GPIO_PIN_6 +#define Z_REF_GPIO_Port GPIOB +#define Y_REF_Pin GPIO_PIN_7 +#define Y_REF_GPIO_Port GPIOB +#define Y_LIM_NEG_Pin GPIO_PIN_8 +#define Y_LIM_NEG_GPIO_Port GPIOB +#define X_REF_Pin GPIO_PIN_9 +#define X_REF_GPIO_Port GPIOB +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +/** + * @} + */ + +/** + * @} +*/ + +#endif /* __MXCONSTANT_H */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ADDED stm32/boards/stm32f405/stm32f405_main.c Index: stm32/boards/stm32f405/stm32f405_main.c ================================================================== --- stm32/boards/stm32f405/stm32f405_main.c +++ stm32/boards/stm32f405/stm32f405_main.c @@ -0,0 +1,459 @@ +/** + ****************************************************************************** + * File Name : main.c + * Description : Main program body + ****************************************************************************** + * + * Copyright (c) 2016 STMicroelectronics International N.V. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted, provided that the following conditions are met: + * + * 1. Redistribution of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of other + * contributors to this software may be used to endorse or promote products + * derived from this software without specific written permission. + * 4. This software, including modifications and/or derivative works of this + * software, must execute solely and exclusively on microcontroller or + * microprocessor devices manufactured by or for STMicroelectronics. + * 5. Redistribution and use of this software other than as permitted under + * this license is void and will automatically terminate your rights under + * this license. + * + * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY + * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT + * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32f4xx_hal.h" +#include "usb_device.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private variables ---------------------------------------------------------*/ +ADC_HandleTypeDef hadc1; + +DAC_HandleTypeDef hdac; + +TIM_HandleTypeDef htim9; +TIM_HandleTypeDef htim14; + +UART_HandleTypeDef huart3; + +/* USER CODE BEGIN PV */ +/* Private variables ---------------------------------------------------------*/ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +void Error_Handler(void); +static void MX_GPIO_Init(void); +static void MX_ADC1_Init(void); +static void MX_DAC_Init(void); +static void MX_TIM14_Init(void); +static void MX_USART3_UART_Init(void); +static void MX_TIM9_Init(void); + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + + +/* USER CODE BEGIN PFP */ +/* Private function prototypes -----------------------------------------------*/ + +/* USER CODE END PFP */ + +/* USER CODE BEGIN 0 */ +int init_stm32f405h(void) +{ + + /* MCU Configuration----------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* Configure the system clock */ + SystemClock_Config(); + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_ADC1_Init(); + MX_DAC_Init(); + MX_USB_DEVICE_Init(); + MX_TIM14_Init(); + MX_USART3_UART_Init(); + MX_TIM9_Init(); + +} + +/* USER CODE END 0 */ + +int stm32_main(void) +{ + + /* USER CODE BEGIN 1 */ + + /* USER CODE END 1 */ + + /* MCU Configuration----------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* Configure the system clock */ + SystemClock_Config(); + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_ADC1_Init(); + MX_DAC_Init(); + MX_USB_DEVICE_Init(); + MX_TIM14_Init(); + MX_USART3_UART_Init(); + MX_TIM9_Init(); + + /* USER CODE BEGIN 2 */ + + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + + } + /* USER CODE END 3 */ + +} + +/** System Clock Configuration +*/ +void SystemClock_Config(void) +{ + + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_ClkInitTypeDef RCC_ClkInitStruct; + + /**Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /**Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 4; + RCC_OscInitStruct.PLL.PLLN = 168; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 7; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /**Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) + { + Error_Handler(); + } + + /**Configure the Systick interrupt time + */ + HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000); + + /**Configure the Systick + */ + HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); + + /* SysTick_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0); +} + +/* ADC1 init function */ +static void MX_ADC1_Init(void) +{ + + ADC_ChannelConfTypeDef sConfig; + + /**Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion) + */ + hadc1.Instance = ADC1; + hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; + hadc1.Init.Resolution = ADC_RESOLUTION_12B; + hadc1.Init.ScanConvMode = DISABLE; + hadc1.Init.ContinuousConvMode = DISABLE; + hadc1.Init.DiscontinuousConvMode = DISABLE; + hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; + hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; + hadc1.Init.NbrOfConversion = 1; + hadc1.Init.DMAContinuousRequests = DISABLE; + hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; + if (HAL_ADC_Init(&hadc1) != HAL_OK) + { + Error_Handler(); + } + + /**Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time. + */ + sConfig.Channel = ADC_CHANNEL_1; + sConfig.Rank = 1; + sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES; + if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + { + Error_Handler(); + } + +} + +/* DAC init function */ +static void MX_DAC_Init(void) +{ + + DAC_ChannelConfTypeDef sConfig; + + /**DAC Initialization + */ + hdac.Instance = DAC; + if (HAL_DAC_Init(&hdac) != HAL_OK) + { + Error_Handler(); + } + + /**DAC channel OUT1 config + */ + sConfig.DAC_Trigger = DAC_TRIGGER_NONE; + sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE; + if (HAL_DAC_ConfigChannel(&hdac, &sConfig, DAC_CHANNEL_1) != HAL_OK) + { + Error_Handler(); + } + +} + +/* TIM9 init function */ +static void MX_TIM9_Init(void) +{ + + TIM_OC_InitTypeDef sConfigOC; + + htim9.Instance = TIM9; + htim9.Init.Prescaler = 0; + htim9.Init.CounterMode = TIM_COUNTERMODE_UP; + htim9.Init.Period = 16800; + htim9.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + if (HAL_TIM_PWM_Init(&htim9) != HAL_OK) + { + Error_Handler(); + } + + sConfigOC.OCMode = TIM_OCMODE_PWM1; + sConfigOC.Pulse = 0; + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + if (HAL_TIM_PWM_ConfigChannel(&htim9, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) + { + Error_Handler(); + } + + HAL_TIM_MspPostInit(&htim9); + +} + +/* TIM14 init function */ +static void MX_TIM14_Init(void) +{ + + htim14.Instance = TIM14; + htim14.Init.Prescaler = 10000; + htim14.Init.CounterMode = TIM_COUNTERMODE_UP; + htim14.Init.Period = 1680; + htim14.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + if (HAL_TIM_Base_Init(&htim14) != HAL_OK) + { + Error_Handler(); + } + +} + +/* USART3 init function */ +static void MX_USART3_UART_Init(void) +{ + + huart3.Instance = USART3; + huart3.Init.BaudRate = 115200; + huart3.Init.WordLength = UART_WORDLENGTH_8B; + huart3.Init.StopBits = UART_STOPBITS_1; + huart3.Init.Parity = UART_PARITY_NONE; + huart3.Init.Mode = UART_MODE_TX_RX; + huart3.Init.HwFlowCtl = UART_HWCONTROL_RTS_CTS; + huart3.Init.OverSampling = UART_OVERSAMPLING_16; + if (HAL_UART_Init(&huart3) != HAL_OK) + { + Error_Handler(); + } + +} + +/** Configure pins as + * Analog + * Input + * Output + * EVENT_OUT + * EXTI +*/ +static void MX_GPIO_Init(void) +{ + + GPIO_InitTypeDef GPIO_InitStruct; + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOC, X_STEP_Pin|Y_STEP_Pin|Z_STEP_Pin|X_DIR_Pin + |Y_DIR_Pin|Z_DIR_Pin|X_EN_Pin|Y_EN_Pin + |Z_EN_Pin|LASER_PSU_Pin|DISC_Pin|LED_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOA, MOTOR_PSU_Pin|MOTOR_PWR_Pin|LASER_KEY_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pins : X_STEP_Pin Y_STEP_Pin Z_STEP_Pin X_DIR_Pin + Y_DIR_Pin Z_DIR_Pin X_EN_Pin Y_EN_Pin + Z_EN_Pin LED_Pin */ + GPIO_InitStruct.Pin = X_STEP_Pin|Y_STEP_Pin|Z_STEP_Pin|X_DIR_Pin + |Y_DIR_Pin|Z_DIR_Pin|X_EN_Pin|Y_EN_Pin + |Z_EN_Pin|LED_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /*Configure GPIO pins : BUT_Pin ALRM_SENSE_Pin LLOCK_SENSE_Pin */ + GPIO_InitStruct.Pin = BUT_Pin|ALRM_SENSE_Pin|LLOCK_SENSE_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_PULLUP; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /*Configure GPIO pin : EMISSION_SENSE_Pin */ + GPIO_InitStruct.Pin = EMISSION_SENSE_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_PULLDOWN; + HAL_GPIO_Init(EMISSION_SENSE_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pin : USB_P_Pin */ + GPIO_InitStruct.Pin = USB_P_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_PULLUP; + HAL_GPIO_Init(USB_P_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pins : X_LIM_POS_Pin X_LIM_NEG_Pin Z_LIM_NEG_Pin Z_LIM_POS_Pin + Y_LIM_POS_Pin Z_REF_Pin Y_REF_Pin Y_LIM_NEG_Pin + X_REF_Pin */ + GPIO_InitStruct.Pin = X_LIM_POS_Pin|X_LIM_NEG_Pin|Z_LIM_NEG_Pin|Z_LIM_POS_Pin + |Y_LIM_POS_Pin|Z_REF_Pin|Y_REF_Pin|Y_LIM_NEG_Pin + |X_REF_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_PULLDOWN; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /*Configure GPIO pins : MOTOR_PSU_Pin MOTOR_PWR_Pin LASER_KEY_Pin */ + GPIO_InitStruct.Pin = MOTOR_PSU_Pin|MOTOR_PWR_Pin|LASER_KEY_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /*Configure GPIO pins : LASER_PSU_Pin DISC_Pin */ + GPIO_InitStruct.Pin = LASER_PSU_Pin|DISC_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @param None + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler */ + /* User can add his own implementation to report the HAL error return state */ + while(1) + { + } + /* USER CODE END Error_Handler */ +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ + +} + +#endif + +/** + * @} + */ + +/** + * @} +*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ADDED stm32/boards/stm32f405/stm32f4xx_hal_conf.h Index: stm32/boards/stm32f405/stm32f4xx_hal_conf.h ================================================================== --- stm32/boards/stm32f405/stm32f4xx_hal_conf.h +++ stm32/boards/stm32f405/stm32f4xx_hal_conf.h @@ -0,0 +1,441 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_conf.h + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_CONF_H +#define __STM32F4xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "main.h" +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED + +#define HAL_ADC_MODULE_ENABLED +/* #define HAL_CAN_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +#define HAL_DAC_MODULE_ENABLED +/* #define HAL_DCMI_MODULE_ENABLED */ +/* #define HAL_DMA2D_MODULE_ENABLED */ +/* #define HAL_ETH_MODULE_ENABLED */ +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_PCCARD_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +/* #define HAL_SDRAM_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ +/* #define HAL_I2C_MODULE_ENABLED */ +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_LTDC_MODULE_ENABLED */ +/* #define HAL_RNG_MODULE_ENABLED */ +/* #define HAL_RTC_MODULE_ENABLED */ +/* #define HAL_SAI_MODULE_ENABLED */ +/* #define HAL_SD_MODULE_ENABLED */ +/* #define HAL_SPI_MODULE_ENABLED */ +#define HAL_TIM_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +#define HAL_PCD_MODULE_ENABLED +/* #define HAL_HCD_MODULE_ENABLED */ +/* #define HAL_DSI_MODULE_ENABLED */ +/* #define HAL_QSPI_MODULE_ENABLED */ +/* #define HAL_QSPI_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_FMPI2C_MODULE_ENABLED */ +/* #define HAL_SPDIFRX_MODULE_ENABLED */ +/* #define HAL_DFSDM_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the External audio frequency in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 1U +#define INSTRUCTION_CACHE_ENABLE 1U +#define DATA_CACHE_ENABLE 1U + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 2U +#define MAC_ADDR1 0U +#define MAC_ADDR2 0U +#define MAC_ADDR3 0U +#define MAC_ADDR4 0U +#define MAC_ADDR5 0U + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* DP83848_PHY_ADDRESS Address*/ +#define DP83848_PHY_ADDRESS 0x01U +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY ((uint32_t)0x000000FFU) +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) + +#define PHY_READ_TO ((uint32_t)0x0000FFFFU) +#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU) + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ +#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ + +#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f4xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f4xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f4xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f4xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f4xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f4xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f4xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32f4xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32f4xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f4xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32f4xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32f4xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f4xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32f4xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32f4xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32f4xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_PCCARD_MODULE_ENABLED + #include "stm32f4xx_hal_pccard.h" +#endif /* HAL_PCCARD_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32f4xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32f4xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f4xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f4xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f4xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32f4xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f4xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32f4xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f4xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32f4xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32f4xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f4xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f4xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f4xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f4xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f4xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f4xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f4xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f4xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32f4xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32f4xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32f4xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32f4xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_FMPI2C_MODULE_ENABLED + #include "stm32f4xx_hal_fmpi2c.h" +#endif /* HAL_FMPI2C_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32f4xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32f4xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32f4xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_CONF_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ADDED stm32/boards/stm32f405/stm32f4xx_hal_msp.c Index: stm32/boards/stm32f405/stm32f4xx_hal_msp.c ================================================================== --- stm32/boards/stm32f405/stm32f4xx_hal_msp.c +++ stm32/boards/stm32f405/stm32f4xx_hal_msp.c @@ -0,0 +1,364 @@ +/** + ****************************************************************************** + * File Name : stm32f4xx_hal_msp.c + * Description : This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * + * Copyright (c) 2016 STMicroelectronics International N.V. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted, provided that the following conditions are met: + * + * 1. Redistribution of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of other + * contributors to this software may be used to endorse or promote products + * derived from this software without specific written permission. + * 4. This software, including modifications and/or derivative works of this + * software, must execute solely and exclusively on microcontroller or + * microprocessor devices manufactured by or for STMicroelectronics. + * 5. Redistribution and use of this software other than as permitted under + * this license is void and will automatically terminate your rights under + * this license. + * + * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY + * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT + * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +extern void Error_Handler(void); +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + + /* System interrupt init*/ + /* MemoryManagement_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(MemoryManagement_IRQn, 0, 0); + /* BusFault_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(BusFault_IRQn, 0, 0); + /* UsageFault_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(UsageFault_IRQn, 0, 0); + /* SVCall_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(SVCall_IRQn, 0, 0); + /* DebugMonitor_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DebugMonitor_IRQn, 0, 0); + /* PendSV_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(PendSV_IRQn, 0, 0); + /* SysTick_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0); + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) +{ + + GPIO_InitTypeDef GPIO_InitStruct; + if(hadc->Instance==ADC1) + { + /* USER CODE BEGIN ADC1_MspInit 0 */ + + /* USER CODE END ADC1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_ADC1_CLK_ENABLE(); + + /**ADC1 GPIO Configuration + PA1 ------> ADC1_IN1 + PA2 ------> ADC1_IN2 + */ + GPIO_InitStruct.Pin = LASER_POWER_MONITOR_Pin|DIODE_CURRENT_MONITOR_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN ADC1_MspInit 1 */ + + /* USER CODE END ADC1_MspInit 1 */ + } + +} + +void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) +{ + + if(hadc->Instance==ADC1) + { + /* USER CODE BEGIN ADC1_MspDeInit 0 */ + + /* USER CODE END ADC1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_ADC1_CLK_DISABLE(); + + /**ADC1 GPIO Configuration + PA1 ------> ADC1_IN1 + PA2 ------> ADC1_IN2 + */ + HAL_GPIO_DeInit(GPIOA, LASER_POWER_MONITOR_Pin|DIODE_CURRENT_MONITOR_Pin); + + } + /* USER CODE BEGIN ADC1_MspDeInit 1 */ + + /* USER CODE END ADC1_MspDeInit 1 */ + +} + +void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac) +{ + + GPIO_InitTypeDef GPIO_InitStruct; + if(hdac->Instance==DAC) + { + /* USER CODE BEGIN DAC_MspInit 0 */ + + /* USER CODE END DAC_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_DAC_CLK_ENABLE(); + + /**DAC GPIO Configuration + PA4 ------> DAC_OUT1 + */ + GPIO_InitStruct.Pin = LASER_POWER_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(LASER_POWER_GPIO_Port, &GPIO_InitStruct); + + /* USER CODE BEGIN DAC_MspInit 1 */ + + /* USER CODE END DAC_MspInit 1 */ + } + +} + +void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac) +{ + + if(hdac->Instance==DAC) + { + /* USER CODE BEGIN DAC_MspDeInit 0 */ + + /* USER CODE END DAC_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_DAC_CLK_DISABLE(); + + /**DAC GPIO Configuration + PA4 ------> DAC_OUT1 + */ + HAL_GPIO_DeInit(LASER_POWER_GPIO_Port, LASER_POWER_Pin); + + } + /* USER CODE BEGIN DAC_MspDeInit 1 */ + + /* USER CODE END DAC_MspDeInit 1 */ + +} + +void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm) +{ + + if(htim_pwm->Instance==TIM9) + { + /* USER CODE BEGIN TIM9_MspInit 0 */ + + /* USER CODE END TIM9_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM9_CLK_ENABLE(); + /* USER CODE BEGIN TIM9_MspInit 1 */ + + /* USER CODE END TIM9_MspInit 1 */ + } + +} + +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) +{ + + if(htim_base->Instance==TIM14) + { + /* USER CODE BEGIN TIM14_MspInit 0 */ + + /* USER CODE END TIM14_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM14_CLK_ENABLE(); + /* Peripheral interrupt init */ + HAL_NVIC_SetPriority(TIM8_TRG_COM_TIM14_IRQn, 1, 0); + HAL_NVIC_EnableIRQ(TIM8_TRG_COM_TIM14_IRQn); + /* USER CODE BEGIN TIM14_MspInit 1 */ + + /* USER CODE END TIM14_MspInit 1 */ + } + +} + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) +{ + + GPIO_InitTypeDef GPIO_InitStruct; + if(htim->Instance==TIM9) + { + /* USER CODE BEGIN TIM9_MspPostInit 0 */ + + /* USER CODE END TIM9_MspPostInit 0 */ + + /**TIM9 GPIO Configuration + PA3 ------> TIM9_CH2 + */ + GPIO_InitStruct.Pin = GPIO_PIN_3; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF3_TIM9; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN TIM9_MspPostInit 1 */ + + /* USER CODE END TIM9_MspPostInit 1 */ + } + +} + +void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef* htim_pwm) +{ + + if(htim_pwm->Instance==TIM9) + { + /* USER CODE BEGIN TIM9_MspDeInit 0 */ + + /* USER CODE END TIM9_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM9_CLK_DISABLE(); + } + /* USER CODE BEGIN TIM9_MspDeInit 1 */ + + /* USER CODE END TIM9_MspDeInit 1 */ + +} + +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base) +{ + + if(htim_base->Instance==TIM14) + { + /* USER CODE BEGIN TIM14_MspDeInit 0 */ + + /* USER CODE END TIM14_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM14_CLK_DISABLE(); + + /* Peripheral interrupt DeInit*/ + HAL_NVIC_DisableIRQ(TIM8_TRG_COM_TIM14_IRQn); + + } + /* USER CODE BEGIN TIM14_MspDeInit 1 */ + + /* USER CODE END TIM14_MspDeInit 1 */ + +} + +void HAL_UART_MspInit(UART_HandleTypeDef* huart) +{ + + GPIO_InitTypeDef GPIO_InitStruct; + if(huart->Instance==USART3) + { + /* USER CODE BEGIN USART3_MspInit 0 */ + + /* USER CODE END USART3_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_USART3_CLK_ENABLE(); + + /**USART3 GPIO Configuration + PB10 ------> USART3_TX + PB11 ------> USART3_RX + PB13 ------> USART3_CTS + PB14 ------> USART3_RTS + */ + GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART3; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART3; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN USART3_MspInit 1 */ + + /* USER CODE END USART3_MspInit 1 */ + } + +} + +void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) +{ + + if(huart->Instance==USART3) + { + /* USER CODE BEGIN USART3_MspDeInit 0 */ + + /* USER CODE END USART3_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART3_CLK_DISABLE(); + + /**USART3 GPIO Configuration + PB10 ------> USART3_TX + PB11 ------> USART3_RX + PB13 ------> USART3_CTS + PB14 ------> USART3_RTS + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_13|GPIO_PIN_14); + + } + /* USER CODE BEGIN USART3_MspDeInit 1 */ + + /* USER CODE END USART3_MspDeInit 1 */ + +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ADDED stm32/boards/stm32f405/stm32f4xx_it.c Index: stm32/boards/stm32f405/stm32f4xx_it.c ================================================================== --- stm32/boards/stm32f405/stm32f4xx_it.c +++ stm32/boards/stm32f405/stm32f4xx_it.c @@ -0,0 +1,220 @@ +/** + ****************************************************************************** + * @file stm32f4xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * + * COPYRIGHT(c) 2016 STMicroelectronics + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" +#include "stm32f4xx.h" +#include "stm32f4xx_it.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +extern PCD_HandleTypeDef hpcd_USB_OTG_FS; +extern TIM_HandleTypeDef htim14; + +/******************************************************************************/ +/* Cortex-M4 Processor Interruption and Exception Handlers */ +/******************************************************************************/ + +/** +* @brief This function handles Non maskable interrupt. +*/ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** +* @brief This function handles Hard fault interrupt. +*/ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + } + /* USER CODE BEGIN HardFault_IRQn 1 */ + + /* USER CODE END HardFault_IRQn 1 */ +} + +/** +* @brief This function handles Memory management fault. +*/ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + } + /* USER CODE BEGIN MemoryManagement_IRQn 1 */ + + /* USER CODE END MemoryManagement_IRQn 1 */ +} + +/** +* @brief This function handles Pre-fetch fault, memory access fault. +*/ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + } + /* USER CODE BEGIN BusFault_IRQn 1 */ + + /* USER CODE END BusFault_IRQn 1 */ +} + +/** +* @brief This function handles Undefined instruction or illegal state. +*/ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + } + /* USER CODE BEGIN UsageFault_IRQn 1 */ + + /* USER CODE END UsageFault_IRQn 1 */ +} + +/** +* @brief This function handles System service call via SWI instruction. +*/ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn 0 */ + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + +/** +* @brief This function handles Debug monitor. +*/ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/** +* @brief This function handles Pendable request for system service. +*/ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** +* @brief This function handles System tick timer. +*/ + +// void SysTick_Handler(void) +// { +// /* USER CODE BEGIN SysTick_IRQn 0 */ +// +// /* USER CODE END SysTick_IRQn 0 */ +// HAL_IncTick(); +// HAL_SYSTICK_IRQHandler(); +// /* USER CODE BEGIN SysTick_IRQn 1 */ +// +// /* USER CODE END SysTick_IRQn 1 */ +// } + +/******************************************************************************/ +/* STM32F4xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32f4xx.s). */ +/******************************************************************************/ + +/** +* @brief This function handles TIM8 trigger and commutation interrupts and TIM14 global interrupt. +*/ +void TIM8_TRG_COM_TIM14_IRQHandler(void) +{ + /* USER CODE BEGIN TIM8_TRG_COM_TIM14_IRQn 0 */ + + /* USER CODE END TIM8_TRG_COM_TIM14_IRQn 0 */ + HAL_TIM_IRQHandler(&htim14); + /* USER CODE BEGIN TIM8_TRG_COM_TIM14_IRQn 1 */ + + /* USER CODE END TIM8_TRG_COM_TIM14_IRQn 1 */ +} + +/** +* @brief This function handles USB On The Go FS global interrupt. +*/ +void OTG_FS_IRQHandler(void) +{ + /* USER CODE BEGIN OTG_FS_IRQn 0 */ + + /* USER CODE END OTG_FS_IRQn 0 */ + HAL_PCD_IRQHandler(&hpcd_USB_OTG_FS); + /* USER CODE BEGIN OTG_FS_IRQn 1 */ + + /* USER CODE END OTG_FS_IRQn 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ADDED stm32/boards/stm32f405/stm32f4xx_it.h Index: stm32/boards/stm32f405/stm32f4xx_it.h ================================================================== --- stm32/boards/stm32f405/stm32f4xx_it.h +++ stm32/boards/stm32f405/stm32f4xx_it.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file stm32f4xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * + * COPYRIGHT(c) 2016 STMicroelectronics + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_IT_H +#define __STM32F4xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void TIM8_TRG_COM_TIM14_IRQHandler(void); +void OTG_FS_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ADDED stm32/boards/stm32f405/usb_device.c Index: stm32/boards/stm32f405/usb_device.c ================================================================== --- stm32/boards/stm32f405/usb_device.c +++ stm32/boards/stm32f405/usb_device.c @@ -0,0 +1,77 @@ +/** + ****************************************************************************** + * @file : USB_DEVICE + * @version : v1.0_Cube + * @brief : This file implements the USB Device + ****************************************************************************** + * + * Copyright (c) 2016 STMicroelectronics International N.V. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted, provided that the following conditions are met: + * + * 1. Redistribution of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of other + * contributors to this software may be used to endorse or promote products + * derived from this software without specific written permission. + * 4. This software, including modifications and/or derivative works of this + * software, must execute solely and exclusively on microcontroller or + * microprocessor devices manufactured by or for STMicroelectronics. + * 5. Redistribution and use of this software other than as permitted under + * this license is void and will automatically terminate your rights under + * this license. + * + * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY + * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT + * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** +*/ + +/* Includes ------------------------------------------------------------------*/ + +#include "usb_device.h" +#include "usbd_core.h" +#include "usbd_desc.h" +#include "usbd_cdc.h" +#include "usbd_cdc_if.h" + +/* USB Device Core handle declaration */ +USBD_HandleTypeDef hUsbDeviceFS; + +/* init function */ +void MX_USB_DEVICE_Init(void) +{ + /* Init Device Library,Add Supported Class and Start the library*/ + USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS); + + USBD_RegisterClass(&hUsbDeviceFS, &USBD_CDC); + + USBD_CDC_RegisterInterface(&hUsbDeviceFS, &USBD_Interface_fops_FS); + + USBD_Start(&hUsbDeviceFS); + +} +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ADDED stm32/boards/stm32f405/usb_device.h Index: stm32/boards/stm32f405/usb_device.h ================================================================== --- stm32/boards/stm32f405/usb_device.h +++ stm32/boards/stm32f405/usb_device.h @@ -0,0 +1,74 @@ +/** + ****************************************************************************** + * @file : USB_DEVICE + * @version : v1.0_Cube + * @brief : Header for usb_device file. + ****************************************************************************** + * + * Copyright (c) 2016 STMicroelectronics International N.V. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted, provided that the following conditions are met: + * + * 1. Redistribution of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of other + * contributors to this software may be used to endorse or promote products + * derived from this software without specific written permission. + * 4. This software, including modifications and/or derivative works of this + * software, must execute solely and exclusively on microcontroller or + * microprocessor devices manufactured by or for STMicroelectronics. + * 5. Redistribution and use of this software other than as permitted under + * this license is void and will automatically terminate your rights under + * this license. + * + * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY + * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT + * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** +*/ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __usb_device_H +#define __usb_device_H +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" +#include "stm32f4xx_hal.h" +#include "usbd_def.h" + +extern USBD_HandleTypeDef hUsbDeviceFS; + +/* USB_Device init function */ +void MX_USB_DEVICE_Init(void); + +#ifdef __cplusplus +} +#endif +#endif /*__usb_device_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ADDED stm32/boards/stm32f405/usbd_cdc_if.c Index: stm32/boards/stm32f405/usbd_cdc_if.c ================================================================== --- stm32/boards/stm32f405/usbd_cdc_if.c +++ stm32/boards/stm32f405/usbd_cdc_if.c @@ -0,0 +1,309 @@ +/** + ****************************************************************************** + * @file : usbd_cdc_if.c + * @brief : + ****************************************************************************** + * + * Copyright (c) 2016 STMicroelectronics International N.V. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted, provided that the following conditions are met: + * + * 1. Redistribution of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of other + * contributors to this software may be used to endorse or promote products + * derived from this software without specific written permission. + * 4. This software, including modifications and/or derivative works of this + * software, must execute solely and exclusively on microcontroller or + * microprocessor devices manufactured by or for STMicroelectronics. + * 5. Redistribution and use of this software other than as permitted under + * this license is void and will automatically terminate your rights under + * this license. + * + * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY + * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT + * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** +*/ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_cdc_if.h" +/* USER CODE BEGIN INCLUDE */ +/* USER CODE END INCLUDE */ + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USBD_CDC + * @brief usbd core module + * @{ + */ + +/** @defgroup USBD_CDC_Private_TypesDefinitions + * @{ + */ +/* USER CODE BEGIN PRIVATE_TYPES */ +/* USER CODE END PRIVATE_TYPES */ +/** + * @} + */ + +/** @defgroup USBD_CDC_Private_Defines + * @{ + */ +/* USER CODE BEGIN PRIVATE_DEFINES */ +/* Define size for the receive and transmit buffer over CDC */ +/* It's up to user to redefine and/or remove those define */ +#define APP_RX_DATA_SIZE 4 +#define APP_TX_DATA_SIZE 4 +/* USER CODE END PRIVATE_DEFINES */ +/** + * @} + */ + +/** @defgroup USBD_CDC_Private_Macros + * @{ + */ +/* USER CODE BEGIN PRIVATE_MACRO */ +/* USER CODE END PRIVATE_MACRO */ + +/** + * @} + */ + +/** @defgroup USBD_CDC_Private_Variables + * @{ + */ +/* Create buffer for reception and transmission */ +/* It's up to user to redefine and/or remove those define */ +/* Received Data over USB are stored in this buffer */ +uint8_t UserRxBufferFS[APP_RX_DATA_SIZE]; + +/* Send Data over USB CDC are stored in this buffer */ +uint8_t UserTxBufferFS[APP_TX_DATA_SIZE]; + +/* USER CODE BEGIN PRIVATE_VARIABLES */ +/* USER CODE END PRIVATE_VARIABLES */ + +/** + * @} + */ + +/** @defgroup USBD_CDC_IF_Exported_Variables + * @{ + */ + extern USBD_HandleTypeDef hUsbDeviceFS; +/* USER CODE BEGIN EXPORTED_VARIABLES */ +/* USER CODE END EXPORTED_VARIABLES */ + +/** + * @} + */ + +/** @defgroup USBD_CDC_Private_FunctionPrototypes + * @{ + */ +static int8_t CDC_Init_FS (void); +static int8_t CDC_DeInit_FS (void); +static int8_t CDC_Control_FS (uint8_t cmd, uint8_t* pbuf, uint16_t length); +static int8_t CDC_Receive_FS (uint8_t* pbuf, uint32_t *Len); + +/* USER CODE BEGIN PRIVATE_FUNCTIONS_DECLARATION */ +/* USER CODE END PRIVATE_FUNCTIONS_DECLARATION */ + +/** + * @} + */ + +USBD_CDC_ItfTypeDef USBD_Interface_fops_FS = +{ + CDC_Init_FS, + CDC_DeInit_FS, + CDC_Control_FS, + CDC_Receive_FS +}; + +/* Private functions ---------------------------------------------------------*/ +/** + * @brief CDC_Init_FS + * Initializes the CDC media low layer over the FS USB IP + * @param None + * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t CDC_Init_FS(void) +{ + /* USER CODE BEGIN 3 */ + /* Set Application Buffers */ + USBD_CDC_SetTxBuffer(&hUsbDeviceFS, UserTxBufferFS, 0); + USBD_CDC_SetRxBuffer(&hUsbDeviceFS, UserRxBufferFS); + USBD_CDC_ReceivePacket(&hUsbDeviceFS); + + return (USBD_OK); + /* USER CODE END 3 */ +} + +/** + * @brief CDC_DeInit_FS + * DeInitializes the CDC media low layer + * @param None + * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t CDC_DeInit_FS(void) +{ + /* USER CODE BEGIN 4 */ + return (USBD_OK); + /* USER CODE END 4 */ +} + +/** + * @brief CDC_Control_FS + * Manage the CDC class requests + * @param cmd: Command code + * @param pbuf: Buffer containing command data (request parameters) + * @param length: Number of data to be sent (in bytes) + * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t CDC_Control_FS (uint8_t cmd, uint8_t* pbuf, uint16_t length) +{ + /* USER CODE BEGIN 5 */ + switch (cmd) + { + case CDC_SEND_ENCAPSULATED_COMMAND: + + break; + + case CDC_GET_ENCAPSULATED_RESPONSE: + + break; + + case CDC_SET_COMM_FEATURE: + + break; + + case CDC_GET_COMM_FEATURE: + + break; + + case CDC_CLEAR_COMM_FEATURE: + + break; + + /*******************************************************************************/ + /* Line Coding Structure */ + /*-----------------------------------------------------------------------------*/ + /* Offset | Field | Size | Value | Description */ + /* 0 | dwDTERate | 4 | Number |Data terminal rate, in bits per second*/ + /* 4 | bCharFormat | 1 | Number | Stop bits */ + /* 0 - 1 Stop bit */ + /* 1 - 1.5 Stop bits */ + /* 2 - 2 Stop bits */ + /* 5 | bParityType | 1 | Number | Parity */ + /* 0 - None */ + /* 1 - Odd */ + /* 2 - Even */ + /* 3 - Mark */ + /* 4 - Space */ + /* 6 | bDataBits | 1 | Number Data bits (5, 6, 7, 8 or 16). */ + /*******************************************************************************/ + case CDC_SET_LINE_CODING: + + break; + + case CDC_GET_LINE_CODING: + + break; + + case CDC_SET_CONTROL_LINE_STATE: + + break; + + case CDC_SEND_BREAK: + + break; + + default: + break; + } + + return (USBD_OK); + /* USER CODE END 5 */ +} + +/** + * @brief CDC_Receive_FS + * Data received over USB OUT endpoint are sent over CDC interface + * through this function. + * + * @note + * This function will block any OUT packet reception on USB endpoint + * untill exiting this function. If you exit this function before transfer + * is complete on CDC interface (ie. using DMA controller) it will result + * in receiving more data while previous ones are still not sent. + * + * @param Buf: Buffer of data to be received + * @param Len: Number of data received (in bytes) + * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t CDC_Receive_FS (uint8_t* Buf, uint32_t *Len) +{ + /* USER CODE BEGIN 6 */ + USBD_CDC_SetRxBuffer(&hUsbDeviceFS, &Buf[0]); + USBD_CDC_ReceivePacket(&hUsbDeviceFS); + return (USBD_OK); + /* USER CODE END 6 */ +} + +/** + * @brief CDC_Transmit_FS + * Data send over USB IN endpoint are sent over CDC interface + * through this function. + * @note + * + * + * @param Buf: Buffer of data to be send + * @param Len: Number of data to be send (in bytes) + * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL or USBD_BUSY + */ +uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len) +{ + uint8_t result = USBD_OK; + /* USER CODE BEGIN 7 */ + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*)hUsbDeviceFS.pClassData; + if (hcdc->TxState != 0){ + return USBD_BUSY; + } + USBD_CDC_SetTxBuffer(&hUsbDeviceFS, Buf, Len); + result = USBD_CDC_TransmitPacket(&hUsbDeviceFS); + /* USER CODE END 7 */ + return result; +} + +/* USER CODE BEGIN PRIVATE_FUNCTIONS_IMPLEMENTATION */ +/* USER CODE END PRIVATE_FUNCTIONS_IMPLEMENTATION */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + ADDED stm32/boards/stm32f405/usbd_cdc_if.h Index: stm32/boards/stm32f405/usbd_cdc_if.h ================================================================== --- stm32/boards/stm32f405/usbd_cdc_if.h +++ stm32/boards/stm32f405/usbd_cdc_if.h @@ -0,0 +1,132 @@ +/** + ****************************************************************************** + * @file : usbd_cdc_if.h + * @brief : Header for usbd_cdc_if file. + ****************************************************************************** + * + * Copyright (c) 2016 STMicroelectronics International N.V. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted, provided that the following conditions are met: + * + * 1. Redistribution of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of other + * contributors to this software may be used to endorse or promote products + * derived from this software without specific written permission. + * 4. This software, including modifications and/or derivative works of this + * software, must execute solely and exclusively on microcontroller or + * microprocessor devices manufactured by or for STMicroelectronics. + * 5. Redistribution and use of this software other than as permitted under + * this license is void and will automatically terminate your rights under + * this license. + * + * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY + * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT + * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** +*/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_CDC_IF_H +#define __USBD_CDC_IF_H + +#ifdef __cplusplus + extern "C" { +#endif +/* Includes ------------------------------------------------------------------*/ +#include "usbd_cdc.h" +/* USER CODE BEGIN INCLUDE */ +/* USER CODE END INCLUDE */ + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USBD_CDC_IF + * @brief header + * @{ + */ + +/** @defgroup USBD_CDC_IF_Exported_Defines + * @{ + */ +/* USER CODE BEGIN EXPORTED_DEFINES */ +/* USER CODE END EXPORTED_DEFINES */ + +/** + * @} + */ + +/** @defgroup USBD_CDC_IF_Exported_Types + * @{ + */ +/* USER CODE BEGIN EXPORTED_TYPES */ +/* USER CODE END EXPORTED_TYPES */ + +/** + * @} + */ + +/** @defgroup USBD_CDC_IF_Exported_Macros + * @{ + */ +/* USER CODE BEGIN EXPORTED_MACRO */ +/* USER CODE END EXPORTED_MACRO */ + +/** + * @} + */ + +/** @defgroup USBD_AUDIO_IF_Exported_Variables + * @{ + */ +extern USBD_CDC_ItfTypeDef USBD_Interface_fops_FS; + +/* USER CODE BEGIN EXPORTED_VARIABLES */ +/* USER CODE END EXPORTED_VARIABLES */ + +/** + * @} + */ + +/** @defgroup USBD_CDC_IF_Exported_FunctionsPrototype + * @{ + */ +uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len); + +/* USER CODE BEGIN EXPORTED_FUNCTIONS */ +/* USER CODE END EXPORTED_FUNCTIONS */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USBD_CDC_IF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ADDED stm32/boards/stm32f405/usbd_conf.c Index: stm32/boards/stm32f405/usbd_conf.c ================================================================== --- stm32/boards/stm32f405/usbd_conf.c +++ stm32/boards/stm32f405/usbd_conf.c @@ -0,0 +1,544 @@ +/** + ****************************************************************************** + * @file : usbd_conf.c + * @version : v1.0_Cube + * @brief : This file implements the board support package for the USB device library + ****************************************************************************** + * + * Copyright (c) 2016 STMicroelectronics International N.V. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted, provided that the following conditions are met: + * + * 1. Redistribution of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of other + * contributors to this software may be used to endorse or promote products + * derived from this software without specific written permission. + * 4. This software, including modifications and/or derivative works of this + * software, must execute solely and exclusively on microcontroller or + * microprocessor devices manufactured by or for STMicroelectronics. + * 5. Redistribution and use of this software other than as permitted under + * this license is void and will automatically terminate your rights under + * this license. + * + * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY + * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT + * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** +*/ +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" +#include "stm32f4xx_hal.h" +#include "usbd_def.h" +#include "usbd_core.h" + +PCD_HandleTypeDef hpcd_USB_OTG_FS; +void Error_Handler(void); + +/* External functions --------------------------------------------------------*/ +void SystemClock_Config(void); + +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* USER CODE BEGIN 1 */ +/* USER CODE END 1 */ + +/******************************************************************************* + LL Driver Callbacks (PCD -> USB Device Library) +*******************************************************************************/ +/* MSP Init */ + +void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle) +{ + GPIO_InitTypeDef GPIO_InitStruct; + if(pcdHandle->Instance==USB_OTG_FS) + { + /* USER CODE BEGIN USB_OTG_FS_MspInit 0 */ + + /* USER CODE END USB_OTG_FS_MspInit 0 */ + + /**USB_OTG_FS GPIO Configuration + PA11 ------> USB_OTG_FS_DM + PA12 ------> USB_OTG_FS_DP + */ + GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* Peripheral clock enable */ + __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); + + /* Peripheral interrupt init */ + HAL_NVIC_SetPriority(OTG_FS_IRQn, 2, 0); + HAL_NVIC_EnableIRQ(OTG_FS_IRQn); + /* USER CODE BEGIN USB_OTG_FS_MspInit 1 */ + + /* USER CODE END USB_OTG_FS_MspInit 1 */ + } +} + +void HAL_PCD_MspDeInit(PCD_HandleTypeDef* pcdHandle) +{ + if(pcdHandle->Instance==USB_OTG_FS) + { + /* USER CODE BEGIN USB_OTG_FS_MspDeInit 0 */ + + /* USER CODE END USB_OTG_FS_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USB_OTG_FS_CLK_DISABLE(); + + /**USB_OTG_FS GPIO Configuration + PA11 ------> USB_OTG_FS_DM + PA12 ------> USB_OTG_FS_DP + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11|GPIO_PIN_12); + + /* Peripheral interrupt Deinit*/ + HAL_NVIC_DisableIRQ(OTG_FS_IRQn); + + /* USER CODE BEGIN USB_OTG_FS_MspDeInit 1 */ + + /* USER CODE END USB_OTG_FS_MspDeInit 1 */ + } +} + +/** + * @brief Setup stage callback + * @param hpcd: PCD handle + * @retval None + */ +void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) +{ + USBD_LL_SetupStage(hpcd->pData, (uint8_t *)hpcd->Setup); +} + +/** + * @brief Data Out stage callback. + * @param hpcd: PCD handle + * @param epnum: Endpoint Number + * @retval None + */ +void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + USBD_LL_DataOutStage(hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff); +} + +/** + * @brief Data In stage callback.. + * @param hpcd: PCD handle + * @param epnum: Endpoint Number + * @retval None + */ +void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + USBD_LL_DataInStage(hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff); +} + +/** + * @brief SOF callback. + * @param hpcd: PCD handle + * @retval None + */ +void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) +{ + USBD_LL_SOF(hpcd->pData); +} + +/** + * @brief Reset callback. + * @param hpcd: PCD handle + * @retval None + */ +void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) +{ + USBD_SpeedTypeDef speed = USBD_SPEED_FULL; + + /*Set USB Current Speed*/ + switch (hpcd->Init.speed) + { + case PCD_SPEED_HIGH: + speed = USBD_SPEED_HIGH; + break; + case PCD_SPEED_FULL: + speed = USBD_SPEED_FULL; + break; + + default: + speed = USBD_SPEED_FULL; + break; + } + USBD_LL_SetSpeed(hpcd->pData, speed); + + /*Reset Device*/ + USBD_LL_Reset(hpcd->pData); +} + +/** + * @brief Suspend callback. + * When Low power mode is enabled the debug cannot be used (IAR, Keil doesn't support it) + * @param hpcd: PCD handle + * @retval None + */ +void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) +{ + /* Inform USB library that core enters in suspend Mode */ + USBD_LL_Suspend(hpcd->pData); + __HAL_PCD_GATE_PHYCLOCK(hpcd); + /*Enter in STOP mode */ + /* USER CODE BEGIN 2 */ + if (hpcd->Init.low_power_enable) + { + /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register */ + SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); + } + /* USER CODE END 2 */ +} + +/** + * @brief Resume callback. + When Low power mode is enabled the debug cannot be used (IAR, Keil doesn't support it) + * @param hpcd: PCD handle + * @retval None + */ +void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) +{ + /* USER CODE BEGIN 3 */ + /* USER CODE END 3 */ + USBD_LL_Resume(hpcd->pData); +} + +/** + * @brief ISOC Out Incomplete callback. + * @param hpcd: PCD handle + * @param epnum: Endpoint Number + * @retval None + */ +void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + USBD_LL_IsoOUTIncomplete(hpcd->pData, epnum); +} + +/** + * @brief ISOC In Incomplete callback. + * @param hpcd: PCD handle + * @param epnum: Endpoint Number + * @retval None + */ +void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + USBD_LL_IsoINIncomplete(hpcd->pData, epnum); +} + +/** + * @brief Connect callback. + * @param hpcd: PCD handle + * @retval None + */ +void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) +{ + USBD_LL_DevConnected(hpcd->pData); +} + +/** + * @brief Disconnect callback. + * @param hpcd: PCD handle + * @retval None + */ +void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) +{ + USBD_LL_DevDisconnected(hpcd->pData); +} + +/******************************************************************************* + LL Driver Interface (USB Device Library --> PCD) +*******************************************************************************/ +/** + * @brief Initializes the Low Level portion of the Device driver. + * @param pdev: Device handle + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_LL_Init (USBD_HandleTypeDef *pdev) +{ + /* Init USB_IP */ + if (pdev->id == DEVICE_FS) { + /* Link The driver to the stack */ + hpcd_USB_OTG_FS.pData = pdev; + pdev->pData = &hpcd_USB_OTG_FS; + + hpcd_USB_OTG_FS.Instance = USB_OTG_FS; + hpcd_USB_OTG_FS.Init.dev_endpoints = 4; + hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL; + hpcd_USB_OTG_FS.Init.dma_enable = DISABLE; + hpcd_USB_OTG_FS.Init.ep0_mps = DEP0CTL_MPS_64; + hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED; + hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE; + hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE; + hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE; + hpcd_USB_OTG_FS.Init.vbus_sensing_enable = ENABLE; + hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE; + if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK) + { + Error_Handler(); + } + + HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_FS, 0x80); + HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 0, 0x40); + HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x80); + } + return USBD_OK; +} + +/** + * @brief De-Initializes the Low Level portion of the Device driver. + * @param pdev: Device handle + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_LL_DeInit (USBD_HandleTypeDef *pdev) +{ + HAL_PCD_DeInit(pdev->pData); + return USBD_OK; +} + +/** + * @brief Starts the Low Level portion of the Device driver. + * @param pdev: Device handle + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev) +{ + HAL_PCD_Start(pdev->pData); + return USBD_OK; +} + +/** + * @brief Stops the Low Level portion of the Device driver. + * @param pdev: Device handle + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_LL_Stop (USBD_HandleTypeDef *pdev) +{ + HAL_PCD_Stop(pdev->pData); + return USBD_OK; +} + +/** + * @brief Opens an endpoint of the Low Level Driver. + * @param pdev: Device handle + * @param ep_addr: Endpoint Number + * @param ep_type: Endpoint Type + * @param ep_mps: Endpoint Max Packet Size + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_LL_OpenEP (USBD_HandleTypeDef *pdev, + uint8_t ep_addr, + uint8_t ep_type, + uint16_t ep_mps) +{ + + HAL_PCD_EP_Open(pdev->pData, + ep_addr, + ep_mps, + ep_type); + + return USBD_OK; +} + +/** + * @brief Closes an endpoint of the Low Level Driver. + * @param pdev: Device handle + * @param ep_addr: Endpoint Number + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_LL_CloseEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + + HAL_PCD_EP_Close(pdev->pData, ep_addr); + return USBD_OK; +} + +/** + * @brief Flushes an endpoint of the Low Level Driver. + * @param pdev: Device handle + * @param ep_addr: Endpoint Number + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_LL_FlushEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + + HAL_PCD_EP_Flush(pdev->pData, ep_addr); + return USBD_OK; +} + +/** + * @brief Sets a Stall condition on an endpoint of the Low Level Driver. + * @param pdev: Device handle + * @param ep_addr: Endpoint Number + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_LL_StallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + + HAL_PCD_EP_SetStall(pdev->pData, ep_addr); + return USBD_OK; +} + +/** + * @brief Clears a Stall condition on an endpoint of the Low Level Driver. + * @param pdev: Device handle + * @param ep_addr: Endpoint Number + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_LL_ClearStallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + + HAL_PCD_EP_ClrStall(pdev->pData, ep_addr); + return USBD_OK; +} + +/** + * @brief Returns Stall condition. + * @param pdev: Device handle + * @param ep_addr: Endpoint Number + * @retval Stall (1: Yes, 0: No) + */ +uint8_t USBD_LL_IsStallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + PCD_HandleTypeDef *hpcd = pdev->pData; + + if((ep_addr & 0x80) == 0x80) + { + return hpcd->IN_ep[ep_addr & 0x7F].is_stall; + } + else + { + return hpcd->OUT_ep[ep_addr & 0x7F].is_stall; + } +} +/** + * @brief Assigns a USB address to the device. + * @param pdev: Device handle + * @param ep_addr: Endpoint Number + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_LL_SetUSBAddress (USBD_HandleTypeDef *pdev, uint8_t dev_addr) +{ + + HAL_PCD_SetAddress(pdev->pData, dev_addr); + return USBD_OK; +} + +/** + * @brief Transmits data over an endpoint. + * @param pdev: Device handle + * @param ep_addr: Endpoint Number + * @param pbuf: Pointer to data to be sent + * @param size: Data size + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_LL_Transmit (USBD_HandleTypeDef *pdev, + uint8_t ep_addr, + uint8_t *pbuf, + uint16_t size) +{ + + HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size); + return USBD_OK; +} + +/** + * @brief Prepares an endpoint for reception. + * @param pdev: Device handle + * @param ep_addr: Endpoint Number + * @param pbuf: Pointer to data to be received + * @param size: Data size + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, + uint8_t ep_addr, + uint8_t *pbuf, + uint16_t size) +{ + + HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size); + return USBD_OK; +} + +/** + * @brief Returns the last transfered packet size. + * @param pdev: Device handle + * @param ep_addr: Endpoint Number + * @retval Recived Data Size + */ +uint32_t USBD_LL_GetRxDataSize (USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + return HAL_PCD_EP_GetRxCount(pdev->pData, ep_addr); +} + +#if (USBD_LPM_ENABLED == 1) +/** + * @brief HAL_PCDEx_LPM_Callback : Send LPM message to user layer + * @param hpcd: PCD handle + * @param msg: LPM message + * @retval HAL status + */ +void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) +{ + switch ( msg) + { + case PCD_LPM_L0_ACTIVE: + if (hpcd->Init.low_power_enable) + { + SystemClock_Config(); + + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); + } + __HAL_PCD_UNGATE_PHYCLOCK(hpcd); + USBD_LL_Resume(hpcd->pData); + break; + + case PCD_LPM_L1_ACTIVE: + __HAL_PCD_GATE_PHYCLOCK(hpcd); + USBD_LL_Suspend(hpcd->pData); + + /*Enter in STOP mode */ + if (hpcd->Init.low_power_enable) + { + /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register */ + SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); + } + break; + } +} +#endif +/** + * @brief Delays routine for the USB Device Library. + * @param Delay: Delay in ms + * @retval None + */ +void USBD_LL_Delay (uint32_t Delay) +{ + HAL_Delay(Delay); +} +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ADDED stm32/boards/stm32f405/usbd_conf.h Index: stm32/boards/stm32f405/usbd_conf.h ================================================================== --- stm32/boards/stm32f405/usbd_conf.h +++ stm32/boards/stm32f405/usbd_conf.h @@ -0,0 +1,183 @@ +/** + ****************************************************************************** + * @file : usbd_conf.h + * @version : v1.0_Cube + * @brief : Header for usbd_conf file. + ****************************************************************************** + * + * Copyright (c) 2016 STMicroelectronics International N.V. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted, provided that the following conditions are met: + * + * 1. Redistribution of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of other + * contributors to this software may be used to endorse or promote products + * derived from this software without specific written permission. + * 4. This software, including modifications and/or derivative works of this + * software, must execute solely and exclusively on microcontroller or + * microprocessor devices manufactured by or for STMicroelectronics. + * 5. Redistribution and use of this software other than as permitted under + * this license is void and will automatically terminate your rights under + * this license. + * + * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY + * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT + * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** +*/ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_CONF__H__ +#define __USBD_CONF__H__ +#ifdef __cplusplus + extern "C" { +#endif +/* Includes ------------------------------------------------------------------*/ +#include +#include +#include +#include "stm32f4xx.h" +#include "stm32f4xx_hal.h" + +/** @addtogroup USBD_OTG_DRIVER + * @{ + */ + +/** @defgroup USBD_CONF + * @brief usb otg low level driver configuration file + * @{ + */ + +/** @defgroup USBD_CONF_Exported_Defines + * @{ + */ + +/*---------- -----------*/ +#define USBD_MAX_NUM_INTERFACES 1 +/*---------- -----------*/ +#define USBD_MAX_NUM_CONFIGURATION 1 +/*---------- -----------*/ +#define USBD_MAX_STR_DESC_SIZ 512 +/*---------- -----------*/ +#define USBD_SUPPORT_USER_STRING 0 +/*---------- -----------*/ +#define USBD_DEBUG_LEVEL 0 +/*---------- -----------*/ +#define USBD_LPM_ENABLED 0 +/*---------- -----------*/ +#define USBD_SELF_POWERED 1 +/*---------- -----------*/ +#define USBD_CDC_INTERVAL 1000 + +/****************************************/ +/* #define for FS and HS identification */ +#define DEVICE_FS 0 +#define DEVICE_HS 1 + +/** @defgroup USBD_Exported_Macros + * @{ + */ + + /* Memory management macros */ +#define USBD_malloc malloc +#define USBD_free free +#define USBD_memset memset +#define USBD_memcpy memcpy + +#define USBD_Delay HAL_Delay + + /* DEBUG macros */ + +#if (USBD_DEBUG_LEVEL > 0) +#define USBD_UsrLog(...) printf(__VA_ARGS__);\ + printf("\n"); +#else +#define USBD_UsrLog(...) +#endif + + +#if (USBD_DEBUG_LEVEL > 1) + +#define USBD_ErrLog(...) printf("ERROR: ") ;\ + printf(__VA_ARGS__);\ + printf("\n"); +#else +#define USBD_ErrLog(...) +#endif + + +#if (USBD_DEBUG_LEVEL > 2) +#define USBD_DbgLog(...) printf("DEBUG : ") ;\ + printf(__VA_ARGS__);\ + printf("\n"); +#else +#define USBD_DbgLog(...) +#endif + +/** + * @} + */ + + + +/** + * @} + */ + +/** @defgroup USBD_CONF_Exported_Types + * @{ + */ +/** + * @} + */ + +/** @defgroup USBD_CONF_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup USBD_CONF_Exported_Variables + * @{ + */ +/** + * @} + */ + +/** @defgroup USBD_CONF_Exported_FunctionsPrototype + * @{ + */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __USBD_CONF__H__ */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + ADDED stm32/boards/stm32f405/usbd_desc.c Index: stm32/boards/stm32f405/usbd_desc.c ================================================================== --- stm32/boards/stm32f405/usbd_desc.c +++ stm32/boards/stm32f405/usbd_desc.c @@ -0,0 +1,358 @@ +/** + ****************************************************************************** + * @file : usbd_desc.c + * @version : v1.0_Cube + * @brief : This file implements the USB Device descriptors + ****************************************************************************** + * + * Copyright (c) 2016 STMicroelectronics International N.V. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted, provided that the following conditions are met: + * + * 1. Redistribution of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of other + * contributors to this software may be used to endorse or promote products + * derived from this software without specific written permission. + * 4. This software, including modifications and/or derivative works of this + * software, must execute solely and exclusively on microcontroller or + * microprocessor devices manufactured by or for STMicroelectronics. + * 5. Redistribution and use of this software other than as permitted under + * this license is void and will automatically terminate your rights under + * this license. + * + * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY + * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT + * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** +*/ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_core.h" +#include "usbd_desc.h" +#include "usbd_conf.h" + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USBD_DESC + * @brief USBD descriptors module + * @{ + */ + +/** @defgroup USBD_DESC_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + +/** @defgroup USBD_DESC_Private_Defines + * @{ + */ +#define USBD_VID 1155 +#define USBD_LANGID_STRING 1033 +#define USBD_MANUFACTURER_STRING "STMicroelectronics" +#define USBD_PID_FS 22336 +#define USBD_PRODUCT_STRING_FS "STM32 Virtual ComPort" +#define USBD_SERIALNUMBER_STRING_FS "00000000001A" +#define USBD_CONFIGURATION_STRING_FS "CDC Config" +#define USBD_INTERFACE_STRING_FS "CDC Interface" + +#define USB_SIZ_BOS_DESC 0x0C + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0*/ +/** + * @} + */ + +/** @defgroup USBD_DESC_Private_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup USBD_DESC_Private_Variables + * @{ + */ +uint8_t * USBD_FS_DeviceDescriptor( USBD_SpeedTypeDef speed , uint16_t *length); +uint8_t * USBD_FS_LangIDStrDescriptor( USBD_SpeedTypeDef speed , uint16_t *length); +uint8_t * USBD_FS_ManufacturerStrDescriptor ( USBD_SpeedTypeDef speed , uint16_t *length); +uint8_t * USBD_FS_ProductStrDescriptor ( USBD_SpeedTypeDef speed , uint16_t *length); +uint8_t * USBD_FS_SerialStrDescriptor( USBD_SpeedTypeDef speed , uint16_t *length); +uint8_t * USBD_FS_ConfigStrDescriptor( USBD_SpeedTypeDef speed , uint16_t *length); +uint8_t * USBD_FS_InterfaceStrDescriptor( USBD_SpeedTypeDef speed , uint16_t *length); + +#ifdef USB_SUPPORT_USER_STRING_DESC +uint8_t * USBD_FS_USRStringDesc (USBD_SpeedTypeDef speed, uint8_t idx , uint16_t *length); +#endif /* USB_SUPPORT_USER_STRING_DESC */ + +#if (USBD_LPM_ENABLED == 1) +uint8_t *USBD_FS_USR_BOSDescriptor(USBD_SpeedTypeDef speed , uint16_t *length); +#endif + +USBD_DescriptorsTypeDef FS_Desc = +{ + USBD_FS_DeviceDescriptor, + USBD_FS_LangIDStrDescriptor, + USBD_FS_ManufacturerStrDescriptor, + USBD_FS_ProductStrDescriptor, + USBD_FS_SerialStrDescriptor, + USBD_FS_ConfigStrDescriptor, + USBD_FS_InterfaceStrDescriptor, +#if (USBD_LPM_ENABLED == 1) + USBD_FS_USR_BOSDescriptor, +#endif +}; + +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 +#endif +/* USB Standard Device Descriptor */ +__ALIGN_BEGIN uint8_t USBD_FS_DeviceDesc[USB_LEN_DEV_DESC] __ALIGN_END = + { + 0x12, /*bLength */ + USB_DESC_TYPE_DEVICE, /*bDescriptorType*/ +#if (USBD_LPM_ENABLED == 1) + 0x01, /*bcdUSB */ /* changed to USB version 2.01 + in order to support LPM L1 suspend + resume test of USBCV3.0*/ +#else + 0x00, /* bcdUSB */ +#endif + 0x02, + 0x02, /*bDeviceClass*/ + 0x02, /*bDeviceSubClass*/ + 0x00, /*bDeviceProtocol*/ + USB_MAX_EP0_SIZE, /*bMaxPacketSize*/ + LOBYTE(USBD_VID), /*idVendor*/ + HIBYTE(USBD_VID), /*idVendor*/ + LOBYTE(USBD_PID_FS), /*idVendor*/ + HIBYTE(USBD_PID_FS), /*idVendor*/ + 0x00, /*bcdDevice rel. 2.00*/ + 0x02, + USBD_IDX_MFC_STR, /*Index of manufacturer string*/ + USBD_IDX_PRODUCT_STR, /*Index of product string*/ + USBD_IDX_SERIAL_STR, /*Index of serial number string*/ + USBD_MAX_NUM_CONFIGURATION /*bNumConfigurations*/ + } ; +/* USB_DeviceDescriptor */ +/* BOS descriptor */ +#if (USBD_LPM_ENABLED == 1) +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 +#endif +__ALIGN_BEGIN uint8_t USBD_FS_BOSDesc[USB_SIZ_BOS_DESC] __ALIGN_END = +{ + 0x5, + USB_DESC_TYPE_BOS, + 0xC, + 0x0, + 0x1, /* 1 device capability */ + /* device capability*/ + 0x7, + USB_DEVICE_CAPABITY_TYPE, + 0x2, + 0x2, /*LPM capability bit set */ + 0x0, + 0x0, + 0x0 +}; +#endif + +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 +#endif + +/* USB Standard Device Descriptor */ +__ALIGN_BEGIN uint8_t USBD_LangIDDesc[USB_LEN_LANGID_STR_DESC] __ALIGN_END = +{ + USB_LEN_LANGID_STR_DESC, + USB_DESC_TYPE_STRING, + LOBYTE(USBD_LANGID_STRING), + HIBYTE(USBD_LANGID_STRING), +}; + +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 +#endif +__ALIGN_BEGIN uint8_t USBD_StrDesc[USBD_MAX_STR_DESC_SIZ] __ALIGN_END; +/** + * @} + */ + +/** @defgroup USBD_DESC_Private_FunctionPrototypes + * @{ + */ +/** + * @} + */ + +/** @defgroup USBD_DESC_Private_Functions + * @{ + */ + +/** +* @brief USBD_FS_DeviceDescriptor +* return the device descriptor +* @param speed : current device speed +* @param length : pointer to data length variable +* @retval pointer to descriptor buffer +*/ +uint8_t * USBD_FS_DeviceDescriptor( USBD_SpeedTypeDef speed , uint16_t *length) +{ + *length = sizeof(USBD_FS_DeviceDesc); + return USBD_FS_DeviceDesc; +} + +/** +* @brief USBD_FS_LangIDStrDescriptor +* return the LangID string descriptor +* @param speed : current device speed +* @param length : pointer to data length variable +* @retval pointer to descriptor buffer +*/ +uint8_t * USBD_FS_LangIDStrDescriptor( USBD_SpeedTypeDef speed , uint16_t *length) +{ + *length = sizeof(USBD_LangIDDesc); + return USBD_LangIDDesc; +} + +/** +* @brief USBD_FS_ProductStrDescriptor +* return the product string descriptor +* @param speed : current device speed +* @param length : pointer to data length variable +* @retval pointer to descriptor buffer +*/ +uint8_t * USBD_FS_ProductStrDescriptor( USBD_SpeedTypeDef speed , uint16_t *length) +{ + if(speed == 0) + { + USBD_GetString (USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); + } + else + { + USBD_GetString (USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); + } + return USBD_StrDesc; +} + +/** +* @brief USBD_FS_ManufacturerStrDescriptor +* return the manufacturer string descriptor +* @param speed : current device speed +* @param length : pointer to data length variable +* @retval pointer to descriptor buffer +*/ +uint8_t * USBD_FS_ManufacturerStrDescriptor( USBD_SpeedTypeDef speed , uint16_t *length) +{ + USBD_GetString (USBD_MANUFACTURER_STRING, USBD_StrDesc, length); + return USBD_StrDesc; +} + +/** +* @brief USBD_FS_SerialStrDescriptor +* return the serial number string descriptor +* @param speed : current device speed +* @param length : pointer to data length variable +* @retval pointer to descriptor buffer +*/ +uint8_t * USBD_FS_SerialStrDescriptor( USBD_SpeedTypeDef speed , uint16_t *length) +{ + if(speed == USBD_SPEED_HIGH) + { + USBD_GetString (USBD_SERIALNUMBER_STRING_FS, USBD_StrDesc, length); + } + else + { + USBD_GetString (USBD_SERIALNUMBER_STRING_FS, USBD_StrDesc, length); + } + return USBD_StrDesc; +} + +/** +* @brief USBD_FS_ConfigStrDescriptor +* return the configuration string descriptor +* @param speed : current device speed +* @param length : pointer to data length variable +* @retval pointer to descriptor buffer +*/ +uint8_t * USBD_FS_ConfigStrDescriptor( USBD_SpeedTypeDef speed , uint16_t *length) +{ + if(speed == USBD_SPEED_HIGH) + { + USBD_GetString (USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); + } + else + { + USBD_GetString (USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); + } + return USBD_StrDesc; +} + +/** +* @brief USBD_HS_InterfaceStrDescriptor +* return the interface string descriptor +* @param speed : current device speed +* @param length : pointer to data length variable +* @retval pointer to descriptor buffer +*/ +uint8_t * USBD_FS_InterfaceStrDescriptor( USBD_SpeedTypeDef speed , uint16_t *length) +{ + if(speed == 0) + { + USBD_GetString (USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); + } + else + { + USBD_GetString (USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); + } + return USBD_StrDesc; +} +#if (USBD_LPM_ENABLED == 1) +/** + * @brief USBD_FS_USR_BOSDescriptor + * return the BOS descriptor + * @param speed : current device speed + * @param length : pointer to data length variable + * @retval pointer to descriptor buffer + */ +uint8_t *USBD_FS_USR_BOSDescriptor(USBD_SpeedTypeDef speed , uint16_t *length) +{ + *length = sizeof(USBD_FS_BOSDesc); + return (uint8_t*)USBD_FS_BOSDesc; +} +#endif +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ADDED stm32/boards/stm32f405/usbd_desc.h Index: stm32/boards/stm32f405/usbd_desc.h ================================================================== --- stm32/boards/stm32f405/usbd_desc.h +++ stm32/boards/stm32f405/usbd_desc.h @@ -0,0 +1,114 @@ +/** + ****************************************************************************** + * @file : usbd_desc.h + * @version : v1.0_Cube + * @brief : Header for usbd_desc file. + ****************************************************************************** + * + * Copyright (c) 2016 STMicroelectronics International N.V. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted, provided that the following conditions are met: + * + * 1. Redistribution of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of other + * contributors to this software may be used to endorse or promote products + * derived from this software without specific written permission. + * 4. This software, including modifications and/or derivative works of this + * software, must execute solely and exclusively on microcontroller or + * microprocessor devices manufactured by or for STMicroelectronics. + * 5. Redistribution and use of this software other than as permitted under + * this license is void and will automatically terminate your rights under + * this license. + * + * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY + * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT + * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** +*/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_DESC__H__ +#define __USBD_DESC__H__ + +#ifdef __cplusplus + extern "C" { +#endif +/* Includes ------------------------------------------------------------------*/ +#include "usbd_def.h" + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USB_DESC + * @brief general defines for the usb device library file + * @{ + */ + +/** @defgroup USB_DESC_Exported_Defines + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_DESC_Exported_TypesDefinitions + * @{ + */ +/** + * @} + */ + +/** @defgroup USBD_DESC_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup USBD_DESC_Exported_Variables + * @{ + */ +extern USBD_DescriptorsTypeDef FS_Desc; +/** + * @} + */ + +/** @defgroup USBD_DESC_Exported_FunctionsPrototype + * @{ + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __USBD_DESC_H */ + +/** + * @} + */ + +/** +* @} +*/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: stm32/hal/utility/trace.h ================================================================== --- stm32/hal/utility/trace.h +++ stm32/hal/utility/trace.h @@ -8,37 +8,36 @@ #define TRACE_LEVEL_WARNING 3 #define TRACE_LEVEL_ERROR 2 #define TRACE_LEVEL_FATAL 1 #define TRACE_LEVEL_NO_TRACE 0 - #if (TRACE_LEVEL >= TRACE_LEVEL_DEBUG) - #define TRACE_DEBUG(...) { printf("-D- " __VA_ARGS__); printf("\r\n"); } + #define TRACE_DEBUG(...) { printf("-D- " __VA_ARGS__); } #else #define TRACE_DEBUG(...) { } #endif #if (TRACE_LEVEL >= TRACE_LEVEL_INFO) - #define TRACE_INFO(...) { printf("-I- " __VA_ARGS__); printf("\r\n"); } + #define TRACE_INFO(...) { printf("-I- " __VA_ARGS__); } #else #define TRACE_INFO(...) { } #endif #if (TRACE_LEVEL >= TRACE_LEVEL_WARNING) - #define TRACE_WARNING(...) { printf("-W- " __VA_ARGS__); printf("\r\n"); } + #define TRACE_WARNING(...) { printf("-W- " __VA_ARGS__); } #else #define TRACE_WARNING(...) { } #endif #if (TRACE_LEVEL >= TRACE_LEVEL_ERROR) - #define TRACE_ERROR(...) { printf("-E- " __VA_ARGS__); printf("\r\n"); } + #define TRACE_ERROR(...) { printf("-E- " __VA_ARGS__); } #else #define TRACE_ERROR(...) { } #endif #if (TRACE_LEVEL >= TRACE_LEVEL_FATAL) - #define TRACE_FATAL(...) { printf("-F- " __VA_ARGS__); printf("\r\n"); while(1); } + #define TRACE_FATAL(...) { printf("-F- " __VA_ARGS__); while(1); } #else #define TRACE_FATAL(...) { while(1); } #endif #endif ADDED stm32f405.mak Index: stm32f405.mak ================================================================== --- stm32f405.mak +++ stm32f405.mak @@ -0,0 +1,40 @@ +# Target CPU architecture: cortex-m3, cortex-m4 +ARCH = cortex-m4 + +# Target part: none, sam3n4, etc. +PART = stm32f405 +CHIP = stm32f405 +BOARD = STM32F405H + +# Application target name. Given with suffix .a for library and .elf for a +# standalone application. +TARGET_FLASH = stm32f405h_flash.elf +TARGET_SRAM = stm32f405h_sram.elf + + +INCLUDES += -Istm32/boards +INCLUDES += -Istm32/boards/stm32f405 +INCLUDES += -Istm32/CMSIS/Device/ST/STM32F4xx/Include +INCLUDES += -Istm32/CMSIS/Include +INCLUDES += -Istm32/STM32_USB_Device_Library/Class/CDC/Inc +INCLUDES += -Istm32/STM32F4xx_HAL_Driver/Inc +INCLUDES += -Istm32/STM32_USB_Device_Library/Core/Inc +INCLUDES += -Istm32/hal + +CSRCS += stm32/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c +CSRCS += stm32/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c +CSRCS += stm32/STM32_USB_Device_Library/Core/Src/usbd_core.c +CSRCS += stm32/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c +CSRCS += stm32/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c +CSRCS += stm32/boards/stm32f405/usb_device.c +CSRCS += stm32/boards/stm32f405/usbd_cdc_if.c +CSRCS += stm32/boards/stm32f405/usbd_conf.c +CSRCS += stm32/boards/stm32f405/usbd_desc.c +CSRCS += stm32/boards/stm32f405/stm32f4xx_it.c +CSRCS += stm32/boards/stm32f405/stm32f4xx_hal_msp.c +CSRCS += $(wildcard stm32/STM32F4xx_HAL_Driver/Src/*.c) +CSRCS += stm32/boards/stm32f405/stm32f405_main.c + +LINKER_SCRIPT_FLASH = stm32/boards/stm32f405/STM32F405RGTx_FLASH.ld + +ASSRCS += stm32/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f405xx.s DELETED stm32f405.mk Index: stm32f405.mk ================================================================== --- stm32f405.mk +++ stm32f405.mk @@ -1,41 +0,0 @@ -# Target CPU architecture: cortex-m3, cortex-m4 -ARCH = cortex-m4 - -# Target part: none, sam3n4, etc. -PART = stm32f405 -CHIP = stm32f405 -BOARD = STM32F405H - -# Application target name. Given with suffix .a for library and .elf for a -# standalone application. -TARGET_FLASH = stm32f405h_flash.elf -TARGET_SRAM = stm32f405h_sram.elf - - -INCLUDES += -Istm32/boards -INCLUDES += -Istm32/boards/stm32f405 -INCLUDES += -Istm32/CMSIS/Device/ST/STM32F4xx/Include -INCLUDES += -Istm32/CMSIS/Include -INCLUDES += -Istm32/STM32_USB_Device_Library/Class/CDC/Inc -INCLUDES += -Istm32/STM32F4xx_HAL_Driver/Inc -INCLUDES += -Istm32/STM32_USB_Device_Library/Core/Inc -INCLUDES += -Istm32/hal -INCLUDES += -Istm32/Inc - -CPPFLAGS += -DSTM32F405xx - -CSRCS += stm32/hal/usb/usb.c -CSRCS += stm32/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c -CSRCS += stm32/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c -CSRCS += stm32/STM32_USB_Device_Library/Core/Src/usbd_core.c -CSRCS += stm32/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c -CSRCS += stm32/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c -CSRCS += $(wildcard stm32/STM32_USB_Device_Library/Src/*.c) -CSRCS += $(wildcard stm32/STM32F4xx_HAL_Driver/Src/*.c) -CSRCS += $(wildcard stm32/Src/*.c) - -LINKER_SCRIPT_FLASH = stm32/boards/stm32f405/STM32F405RGTx_FLASH.ld - -ASSRCS += stm32/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f405xx.s - -cpuflags-gnu-y += -mfloat-abi=hard -mfpu=fpv4-sp-d16